driver-api: create an edac.rst file with EDAC documentation
Currently, there's no device driver documentation for the EDAC subsystem at the driver-api book. Fill in the blanks for the structures and functions that misses documentation, uniform the word on the existing ones, and add a new edac.rst file at driver-api, in order to document the EDAC subsystem. Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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Documentation/driver-api/edac.rst
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72
Documentation/driver-api/edac.rst
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Error Detection And Correction (EDAC) Devices
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=============================================
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Memory Controllers
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------------------
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Most of the EDAC core is focused on doing Memory Controller error detection.
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The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info``
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to describe the memory controllers, with is an opaque struct for the EDAC
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drivers. Only the EDAC core is allowed to touch it.
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.. kernel-doc:: include/linux/edac.h
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.. kernel-doc:: drivers/edac/edac_mc.h
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PCI Controllers
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---------------
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The EDAC subsystem provides a mechanism to handle PCI controllers by calling
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the :c:func:`edac_pci_alloc_ctl_info`. It will use the struct
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:c:type:`edac_pci_ctl_info` to describe the PCI controllers.
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.. kernel-doc:: drivers/edac/edac_pci.h
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EDAC Blocks
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-----------
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The EDAC subsystem also provides a generic mechanism to report errors on
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other parts of the hardware via :c:func:`edac_device_alloc_ctl_info` function.
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The structures :c:type:`edac_dev_sysfs_block_attribute`,
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:c:type:`edac_device_block`, :c:type:`edac_device_instance` and
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:c:type:`edac_device_ctl_info` provide a generic or abstract 'edac_device'
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representation at sysfs.
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This set of structures and the code that implements the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or
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PCI, like:
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- CPU caches (L1 and L2)
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- DMA engines
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- Core CPU switches
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- Fabric switch units
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- PCIe interface controllers
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- other EDAC/ECC type devices that can be monitored for
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errors, etc.
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It allows for a 2 level set of hierarchy.
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For example, a cache could be composed of L1, L2 and L3 levels of cache.
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Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
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caches. On such case, those can be represented via the following sysfs
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nodes::
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/sys/devices/system/edac/..
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pci/ <existing pci directory (if available)>
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mc/ <existing memory device directory>
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cpu/cpu0/.. <L1 and L2 block directory>
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/L1-cache/ce_count
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/ue_count
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/L2-cache/ce_count
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/ue_count
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cpu/cpu1/.. <L1 and L2 block directory>
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/L1-cache/ce_count
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/ue_count
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/L2-cache/ce_count
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/ue_count
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...
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the L1 and L2 directories would be "edac_device_block's"
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.. kernel-doc:: drivers/edac/edac_device.h
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@ -26,6 +26,7 @@ available subsections can be seen below.
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spi
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i2c
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hsi
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edac
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miscellaneous
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vme
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80211/index
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@ -152,8 +152,6 @@ extern void edac_mc_free(struct mem_ctl_info *mci);
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*
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* If found, return a pointer to the structure.
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* Else return NULL.
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*
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* Caller must hold mem_ctls_mutex.
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*/
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extern struct mem_ctl_info *edac_mc_find(int idx);
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