Merge branches 'clk-hisi', 'clk-amlogic', 'clk-samsung', 'clk-renesas' and 'clk-imx' into clk-next
* clk-hisi: clk: hi6220: use CLK_OF_DECLARE_DRIVER * clk-amlogic: clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code clk: meson: axg_audio: add sm1 support clk: meson: axg-audio: provide clk top signal name clk: meson: axg-audio: prepare sm1 addition clk: meson: axg-audio: fix regmap last register clk: meson: axg-audio: remove useless defines dt-bindings: clock: meson: add sm1 resets to the axg-audio controller dt-bindings: clk: axg-audio: add sm1 bindings clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: g12a: fix cpu clock rate setting clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate * clk-samsung: clk: samsung: exynos5420: Add SET_RATE_PARENT flag to clocks on G3D path clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume clk: samsung: exynos5420: Add VPLL rate table clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU clk: samsung: exynos5433: Fix error paths * clk-renesas: (23 commits) clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 dt-bindings: clock: renesas: cpg-mssr: Document r8a77961 support clk: renesas: r8a77965: Remove superfluous semicolon dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix typo in example dt-bindings: clock: renesas: Remove R-Car Gen2 legacy DT bindings dt-bindings: clock: Add r8a77961 CPG Core Clock Definitions dt-bindings: power: Add r8a77961 SYSC power domain definitions clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate() clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate() clk: renesas: rcar-gen2: Switch Z clock to .determine_rate() clk: renesas: r8a774b1: Add TMU clock clk: renesas: cpg-mssr: Add r8a774b1 support dt-bindings: clock: renesas: cpg-mssr: Document r8a774b1 binding clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate() clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div() clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate() clk: renesas: rcar-gen3: Improve arithmetic divisions clk: renesas: rcar-gen2: Improve arithmetic divisions clk: renesas: Remove R-Car Gen2 legacy DT clock support ... * clk-imx: clk: imx: imx8mq: fix sys3_pll_out_sels clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_PLL clock clk: imx: imx6ul: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sx: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx6sll: use imx_obtain_fixed_clk_hw to simplify code clk: imx: imx7d: use imx_obtain_fixed_clk_hw to simplify code clk: imx7ulp: Correct DDR clock mux options clk: imx7ulp: Correct system clock source option #7 clk: imx: imx8mq: mark sys1/2_pll as fixed clock clk: imx: imx8mn: mark sys_pll1/2 as fixed clock clk: imx: imx8mm: mark sys_pll1/2 as fixed clock clk: imx8mn: Define gates for pll1/2 fixed dividers clk: imx8mm: Define gates for pll1/2 fixed dividers clk: imx8mq: Define gates for pll1/2 fixed dividers clk: imx: clk-pll14xx: Make two variables static clk: imx8mq: Add VIDEO2_PLL clock clk: imx8mn: Use common 1443X/1416X PLL clock structure clk: imx8mm: Move 1443X/1416X PLL clock structure to common place clk: imx: pll14xx: Fix quick switch of S/K parameter5.9.x+fslc
Stephen Boyd
commit
74ca928886
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@ -7,7 +7,8 @@ devices.
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Required Properties:
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- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
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"amlogic,g12a-audio-clkc" for G12A.
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"amlogic,g12a-audio-clkc" for G12A,
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"amlogic,sm1-audio-clkc" for S905X3.
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- reg : physical base address of the clock controller and length of
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memory mapped region.
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- clocks : a list of phandle + clock-specifier pairs for the clocks listed
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@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 {
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<&scg1 IMX7ULP_CLK_APLL_PFD0>,
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<&scg1 IMX7ULP_CLK_UPLL>,
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<&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_MIPI_PLL>,
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<&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
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<&scg1 IMX7ULP_CLK_ROSC>,
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<&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
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@ -19,6 +19,7 @@ Required Properties:
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
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- "renesas,r8a774b1-cpg-mssr" for the r8a774a1 SoC (RZ/G2N)
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- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
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- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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@ -26,7 +27,8 @@ Required Properties:
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- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
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- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
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- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
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- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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@ -40,10 +42,11 @@ Required Properties:
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
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r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
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r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77990,
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r8a77995)
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- "extalr" (r8a774a1, r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)
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r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
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r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
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r8a77980, r8a77990, r8a77995)
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- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
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r8a77970, r8a77980)
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- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
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r8a7793, r8a7794)
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@ -1,60 +0,0 @@
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* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
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and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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and "renesas,rcar-gen2-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to the parent clocks: first to the EXTAL clock, second
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to the USB_EXTAL clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
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"adsp"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk &usb_extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0, "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1", "z",
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"rcan", "adsp";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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power-domains = <&cpg_clocks>;
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};
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@ -46,7 +46,7 @@ Required properties:
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Example (R-Car H3):
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usb2_clksel: clock-controller@e6590630 {
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compatible = "renesas,r8a77950-rcar-usb2-clock-sel",
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compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
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"renesas,rcar-gen3-usb2-clock-sel";
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reg = <0 0xe6590630 0 0x02>;
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clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
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@ -86,7 +86,8 @@ static void __init hi6220_clk_ao_init(struct device_node *np)
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hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
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ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
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}
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CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
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/* Allow reset driver to probe as well */
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CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
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/* clocks in sysctrl */
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@ -107,12 +107,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
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hws[IMX6SLL_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
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hws[IMX6SLL_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
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hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
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hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
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/* ipp_di clock is external input */
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hws[IMX6SLL_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
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hws[IMX6SLL_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
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hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
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hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
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base = of_iomap(np, 0);
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@ -139,16 +139,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
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hws[IMX6SX_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
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hws[IMX6SX_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
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hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
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hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
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/* ipp_di clock is external input */
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hws[IMX6SX_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
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hws[IMX6SX_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
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hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
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hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
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/* Clock source from external clock via CLK1/2 PAD */
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hws[IMX6SX_CLK_ANACLK1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "anaclk1"));
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hws[IMX6SX_CLK_ANACLK2] = __clk_get_hw(of_clk_get_by_name(ccm_node, "anaclk2"));
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hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1");
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hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
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base = of_iomap(np, 0);
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@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
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hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
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hws[IMX6UL_CLK_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
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hws[IMX6UL_CLK_OSC] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
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hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
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hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
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/* ipp_di clock is external input */
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hws[IMX6UL_CLK_IPP_DI0] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di0"));
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hws[IMX6UL_CLK_IPP_DI1] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ipp_di1"));
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hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
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hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
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base = of_iomap(np, 0);
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@ -403,8 +403,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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hws = clk_hw_data->hws;
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hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
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hws[IMX7D_OSC_24M_CLK] = __clk_get_hw(of_clk_get_by_name(ccm_node, "osc"));
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hws[IMX7D_CKIL] = __clk_get_hw(of_clk_get_by_name(ccm_node, "ckil"));
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hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
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hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
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base = of_iomap(np, 0);
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@ -24,11 +24,11 @@ static const char * const spll_pfd_sels[] = { "spll_pfd0", "spll_pfd1", "spll_pf
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static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
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static const char * const apll_pfd_sels[] = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
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static const char * const apll_sels[] = { "apll", "apll_pfd_sel", };
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static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "upll", };
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static const char * const ddr_sels[] = { "apll_pfd_sel", "upll", };
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static const char * const scs_sels[] = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "dummy", };
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static const char * const ddr_sels[] = { "apll_pfd_sel", "dummy", "dummy", "dummy", };
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static const char * const nic_sels[] = { "firc", "ddr_clk", };
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static const char * const periph_plat_sels[] = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
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static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
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static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
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static const char * const arm_sels[] = { "divcore", "dummy", "dummy", "hsrun_divcore", };
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/* used by sosc/sirc/firc/ddr/spll/apll dividers */
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@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
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clks[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
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clks[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
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clks[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
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clks[IMX7ULP_CLK_MIPI_PLL] = imx_obtain_fixed_clk_hw(np, "mpll");
|
||||
clks[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
|
||||
|
||||
/* SCG1 */
|
||||
|
|
@ -118,7 +117,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
|
|||
clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
|
||||
clks[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
|
||||
clks[IMX7ULP_CLK_NIC_SEL] = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
|
||||
clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 1, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
clks[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
|
||||
|
||||
clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
|
||||
clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);
|
||||
|
|
|
|||
|
|
@ -26,73 +26,6 @@ static u32 share_count_disp;
|
|||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_videopll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_audiopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_audiopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_videopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_videopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mm_drampll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mm_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mm_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static const char *pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char *audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char *audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
|
|
@ -101,8 +34,6 @@ static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
|
|||
static const char *gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char *vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
|
||||
static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
|
||||
static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
/* CCM ROOT */
|
||||
|
|
@ -392,20 +323,18 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MM_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MM_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mm_audio_pll);
|
||||
clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mm_audio_pll);
|
||||
clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mm_video_pll);
|
||||
clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mm_dram_pll);
|
||||
clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mm_gpu_pll);
|
||||
clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mm_vpu_pll);
|
||||
clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mm_arm_pll);
|
||||
clks[IMX8MM_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mm_sys_pll);
|
||||
clks[IMX8MM_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mm_sys_pll);
|
||||
clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mm_sys_pll);
|
||||
clks[IMX8MM_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
|
||||
clks[IMX8MM_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
|
||||
clks[IMX8MM_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
|
||||
clks[IMX8MM_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll);
|
||||
clks[IMX8MM_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
|
||||
clks[IMX8MM_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
|
||||
clks[IMX8MM_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
|
||||
clks[IMX8MM_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000);
|
||||
clks[IMX8MM_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000);
|
||||
clks[IMX8MM_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MM_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
|
@ -415,8 +344,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MM_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MM_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* PLL out gate */
|
||||
|
|
@ -427,29 +354,48 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MM_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
|
||||
clks[IMX8MM_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
|
||||
clks[IMX8MM_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
|
||||
clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
|
||||
clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
|
||||
clks[IMX8MM_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
|
||||
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
|
||||
clks[IMX8MM_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
|
||||
clks[IMX8MM_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
|
||||
clks[IMX8MM_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
|
||||
clks[IMX8MM_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
|
||||
clks[IMX8MM_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
|
||||
clks[IMX8MM_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
|
||||
clks[IMX8MM_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
|
||||
/* SYS PLL1 fixed output */
|
||||
clks[IMX8MM_SYS_PLL1_40M_CG] = imx_clk_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
|
||||
clks[IMX8MM_SYS_PLL1_80M_CG] = imx_clk_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
|
||||
clks[IMX8MM_SYS_PLL1_100M_CG] = imx_clk_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
|
||||
clks[IMX8MM_SYS_PLL1_133M_CG] = imx_clk_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
|
||||
clks[IMX8MM_SYS_PLL1_160M_CG] = imx_clk_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
|
||||
clks[IMX8MM_SYS_PLL1_200M_CG] = imx_clk_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
|
||||
clks[IMX8MM_SYS_PLL1_266M_CG] = imx_clk_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
|
||||
clks[IMX8MM_SYS_PLL1_400M_CG] = imx_clk_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
|
||||
clks[IMX8MM_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
|
||||
|
||||
clks[IMX8MM_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
|
||||
clks[IMX8MM_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
|
||||
clks[IMX8MM_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
|
||||
clks[IMX8MM_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
|
||||
clks[IMX8MM_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
|
||||
clks[IMX8MM_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
|
||||
clks[IMX8MM_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
|
||||
clks[IMX8MM_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
|
||||
clks[IMX8MM_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
|
||||
|
||||
clks[IMX8MM_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
|
||||
clks[IMX8MM_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
|
||||
clks[IMX8MM_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
|
||||
clks[IMX8MM_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
|
||||
clks[IMX8MM_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
|
||||
clks[IMX8MM_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
|
||||
clks[IMX8MM_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
|
||||
clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
/* SYS PLL2 fixed output */
|
||||
clks[IMX8MM_SYS_PLL2_50M_CG] = imx_clk_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
|
||||
clks[IMX8MM_SYS_PLL2_100M_CG] = imx_clk_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
|
||||
clks[IMX8MM_SYS_PLL2_125M_CG] = imx_clk_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
|
||||
clks[IMX8MM_SYS_PLL2_166M_CG] = imx_clk_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
|
||||
clks[IMX8MM_SYS_PLL2_200M_CG] = imx_clk_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
|
||||
clks[IMX8MM_SYS_PLL2_250M_CG] = imx_clk_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
|
||||
clks[IMX8MM_SYS_PLL2_333M_CG] = imx_clk_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
|
||||
clks[IMX8MM_SYS_PLL2_500M_CG] = imx_clk_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
|
||||
clks[IMX8MM_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
|
||||
|
||||
clks[IMX8MM_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
|
||||
clks[IMX8MM_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
|
||||
clks[IMX8MM_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
|
||||
clks[IMX8MM_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
|
||||
clks[IMX8MM_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
|
||||
clks[IMX8MM_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
|
||||
clks[IMX8MM_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
|
||||
clks[IMX8MM_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
|
||||
clks[IMX8MM_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
|
|
|
|||
|
|
@ -25,75 +25,6 @@ static u32 share_count_disp;
|
|||
static u32 share_count_pdm;
|
||||
static u32 share_count_nand;
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1500000000U, 375, 3, 1),
|
||||
PLL_1416X_RATE(1400000000U, 350, 3, 1),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_audiopll_tbl[] = {
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_videopll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_audio_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_audiopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_video_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_videopll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_dram_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx8mn_drampll_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_arm_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static struct imx_pll14xx_clk imx8mn_sys_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx8mn_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
|
|
@ -102,8 +33,6 @@ static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_se
|
|||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
|
||||
static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
|
||||
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m",
|
||||
|
|
@ -391,20 +320,18 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL1_REF_SEL] = imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL2_REF_SEL] = imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx8mn_audio_pll);
|
||||
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx8mn_video_pll);
|
||||
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx8mn_dram_pll);
|
||||
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx8mn_gpu_pll);
|
||||
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx8mn_vpu_pll);
|
||||
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx8mn_arm_pll);
|
||||
clks[IMX8MN_SYS_PLL1] = imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base + 0x94, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL2] = imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel", base + 0x104, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx8mn_sys_pll);
|
||||
clks[IMX8MN_AUDIO_PLL1] = imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
|
||||
clks[IMX8MN_AUDIO_PLL2] = imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
|
||||
clks[IMX8MN_VIDEO_PLL1] = imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
|
||||
clks[IMX8MN_DRAM_PLL] = imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_pll);
|
||||
clks[IMX8MN_GPU_PLL] = imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
|
||||
clks[IMX8MN_VPU_PLL] = imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
|
||||
clks[IMX8MN_ARM_PLL] = imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
|
||||
clks[IMX8MN_SYS_PLL1] = imx_clk_fixed("sys_pll1", 800000000);
|
||||
clks[IMX8MN_SYS_PLL2] = imx_clk_fixed("sys_pll2", 1000000000);
|
||||
clks[IMX8MN_SYS_PLL3] = imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel", base + 0x114, &imx_1416x_pll);
|
||||
|
||||
/* PLL bypass out */
|
||||
clks[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
|
@ -414,8 +341,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MN_GPU_PLL_BYPASS] = imx_clk_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_VPU_PLL_BYPASS] = imx_clk_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_ARM_PLL_BYPASS] = imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL1_BYPASS] = imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 28, 1, sys_pll1_bypass_sels, ARRAY_SIZE(sys_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL2_BYPASS] = imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 28, 1, sys_pll2_bypass_sels, ARRAY_SIZE(sys_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
clks[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* PLL out gate */
|
||||
|
|
@ -426,29 +351,48 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
|
||||
clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
|
||||
clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
|
||||
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
|
||||
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
|
||||
clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
|
||||
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2);
|
||||
/* SYS PLL1 fixed output */
|
||||
clks[IMX8MN_SYS_PLL1_40M_CG] = imx_clk_gate("sys_pll1_40m_cg", "sys_pll1", base + 0x94, 27);
|
||||
clks[IMX8MN_SYS_PLL1_80M_CG] = imx_clk_gate("sys_pll1_80m_cg", "sys_pll1", base + 0x94, 25);
|
||||
clks[IMX8MN_SYS_PLL1_100M_CG] = imx_clk_gate("sys_pll1_100m_cg", "sys_pll1", base + 0x94, 23);
|
||||
clks[IMX8MN_SYS_PLL1_133M_CG] = imx_clk_gate("sys_pll1_133m_cg", "sys_pll1", base + 0x94, 21);
|
||||
clks[IMX8MN_SYS_PLL1_160M_CG] = imx_clk_gate("sys_pll1_160m_cg", "sys_pll1", base + 0x94, 19);
|
||||
clks[IMX8MN_SYS_PLL1_200M_CG] = imx_clk_gate("sys_pll1_200m_cg", "sys_pll1", base + 0x94, 17);
|
||||
clks[IMX8MN_SYS_PLL1_266M_CG] = imx_clk_gate("sys_pll1_266m_cg", "sys_pll1", base + 0x94, 15);
|
||||
clks[IMX8MN_SYS_PLL1_400M_CG] = imx_clk_gate("sys_pll1_400m_cg", "sys_pll1", base + 0x94, 13);
|
||||
clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1", base + 0x94, 11);
|
||||
|
||||
clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_40m_cg", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL1_80M] = imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_80m_cg", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL1_100M] = imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_100m_cg", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL1_133M] = imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_133m_cg", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL1_160M] = imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_160m_cg", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL1_200M] = imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_200m_cg", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL1_266M] = imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_266m_cg", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL1_400M] = imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_400m_cg", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL1_800M] = imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1);
|
||||
|
||||
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
/* SYS PLL2 fixed output */
|
||||
clks[IMX8MN_SYS_PLL2_50M_CG] = imx_clk_gate("sys_pll2_50m_cg", "sys_pll2", base + 0x104, 27);
|
||||
clks[IMX8MN_SYS_PLL2_100M_CG] = imx_clk_gate("sys_pll2_100m_cg", "sys_pll2", base + 0x104, 25);
|
||||
clks[IMX8MN_SYS_PLL2_125M_CG] = imx_clk_gate("sys_pll2_125m_cg", "sys_pll2", base + 0x104, 23);
|
||||
clks[IMX8MN_SYS_PLL2_166M_CG] = imx_clk_gate("sys_pll2_166m_cg", "sys_pll2", base + 0x104, 21);
|
||||
clks[IMX8MN_SYS_PLL2_200M_CG] = imx_clk_gate("sys_pll2_200m_cg", "sys_pll2", base + 0x104, 19);
|
||||
clks[IMX8MN_SYS_PLL2_250M_CG] = imx_clk_gate("sys_pll2_250m_cg", "sys_pll2", base + 0x104, 17);
|
||||
clks[IMX8MN_SYS_PLL2_333M_CG] = imx_clk_gate("sys_pll2_333m_cg", "sys_pll2", base + 0x104, 15);
|
||||
clks[IMX8MN_SYS_PLL2_500M_CG] = imx_clk_gate("sys_pll2_500m_cg", "sys_pll2", base + 0x104, 13);
|
||||
clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2", base + 0x104, 11);
|
||||
|
||||
clks[IMX8MN_SYS_PLL2_50M] = imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_50m_cg", 1, 20);
|
||||
clks[IMX8MN_SYS_PLL2_100M] = imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_100m_cg", 1, 10);
|
||||
clks[IMX8MN_SYS_PLL2_125M] = imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_125m_cg", 1, 8);
|
||||
clks[IMX8MN_SYS_PLL2_166M] = imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_166m_cg", 1, 6);
|
||||
clks[IMX8MN_SYS_PLL2_200M] = imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_200m_cg", 1, 5);
|
||||
clks[IMX8MN_SYS_PLL2_250M] = imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_250m_cg", 1, 4);
|
||||
clks[IMX8MN_SYS_PLL2_333M] = imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_333m_cg", 1, 3);
|
||||
clks[IMX8MN_SYS_PLL2_500M] = imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_500m_cg", 1, 2);
|
||||
clks[IMX8MN_SYS_PLL2_1000M] = imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
|
|
|
|||
|
|
@ -34,10 +34,9 @@ static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_
|
|||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
|
||||
|
||||
static const char * const sys1_pll_out_sels[] = {"sys1_pll1_ref_sel", };
|
||||
static const char * const sys2_pll_out_sels[] = {"sys1_pll1_ref_sel", "sys2_pll1_ref_sel", };
|
||||
static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", "sys2_pll1_ref_sel", };
|
||||
static const char * const sys3_pll_out_sels[] = {"sys3_pll1_ref_sel", };
|
||||
static const char * const dram_pll_out_sels[] = {"dram_pll1_ref_sel", };
|
||||
static const char * const video2_pll_out_sels[] = {"video2_pll1_ref_sel", };
|
||||
|
||||
/* CCM ROOT */
|
||||
static const char * const imx8mq_a53_sels[] = {"osc_25m", "arm_pll_out", "sys2_pll_500m", "sys2_pll_1000m",
|
||||
|
|
@ -307,10 +306,9 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MQ_AUDIO_PLL1_REF_SEL] = imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_AUDIO_PLL2_REF_SEL] = imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_VIDEO_PLL1_REF_SEL] = imx_clk_mux("video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_SYS1_PLL1_REF_SEL] = imx_clk_mux("sys1_pll1_ref_sel", base + 0x30, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_SYS2_PLL1_REF_SEL] = imx_clk_mux("sys2_pll1_ref_sel", base + 0x3c, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_SYS3_PLL1_REF_SEL] = imx_clk_mux("sys3_pll1_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_DRAM_PLL1_REF_SEL] = imx_clk_mux("dram_pll1_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
clks[IMX8MQ_VIDEO2_PLL1_REF_SEL] = imx_clk_mux("video2_pll1_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
clks[IMX8MQ_ARM_PLL_REF_DIV] = imx_clk_divider("arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6);
|
||||
clks[IMX8MQ_GPU_PLL_REF_DIV] = imx_clk_divider("gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6);
|
||||
|
|
@ -342,30 +340,53 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
clks[IMX8MQ_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x8, 21);
|
||||
clks[IMX8MQ_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x10, 21);
|
||||
|
||||
clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_sccg_pll("sys1_pll_out", sys1_pll_out_sels, ARRAY_SIZE(sys1_pll_out_sels), 0, 0, 0, base + 0x30, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_sccg_pll("sys2_pll_out", sys2_pll_out_sels, ARRAY_SIZE(sys2_pll_out_sels), 0, 0, 1, base + 0x3c, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 1, base + 0x48, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_SYS1_PLL_OUT] = imx_clk_fixed("sys1_pll_out", 800000000);
|
||||
clks[IMX8MQ_SYS2_PLL_OUT] = imx_clk_fixed("sys2_pll_out", 1000000000);
|
||||
clks[IMX8MQ_SYS3_PLL_OUT] = imx_clk_sccg_pll("sys3_pll_out", sys3_pll_out_sels, ARRAY_SIZE(sys3_pll_out_sels), 0, 0, 0, base + 0x48, CLK_IS_CRITICAL);
|
||||
clks[IMX8MQ_DRAM_PLL_OUT] = imx_clk_sccg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL);
|
||||
/* SYS PLL fixed output */
|
||||
clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
|
||||
clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
|
||||
clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);
|
||||
clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);
|
||||
clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);
|
||||
clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);
|
||||
clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);
|
||||
clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
|
||||
clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
|
||||
clks[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_sccg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
|
||||
|
||||
clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
|
||||
clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
|
||||
clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);
|
||||
clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);
|
||||
clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);
|
||||
clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);
|
||||
clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);
|
||||
clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);
|
||||
clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);
|
||||
/* SYS PLL1 fixed output */
|
||||
clks[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);
|
||||
clks[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);
|
||||
clks[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);
|
||||
clks[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);
|
||||
clks[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);
|
||||
clks[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);
|
||||
clks[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);
|
||||
clks[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);
|
||||
clks[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);
|
||||
|
||||
clks[IMX8MQ_SYS1_PLL_40M] = imx_clk_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);
|
||||
clks[IMX8MQ_SYS1_PLL_80M] = imx_clk_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);
|
||||
clks[IMX8MQ_SYS1_PLL_100M] = imx_clk_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);
|
||||
clks[IMX8MQ_SYS1_PLL_133M] = imx_clk_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);
|
||||
clks[IMX8MQ_SYS1_PLL_160M] = imx_clk_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);
|
||||
clks[IMX8MQ_SYS1_PLL_200M] = imx_clk_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);
|
||||
clks[IMX8MQ_SYS1_PLL_266M] = imx_clk_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);
|
||||
clks[IMX8MQ_SYS1_PLL_400M] = imx_clk_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);
|
||||
clks[IMX8MQ_SYS1_PLL_800M] = imx_clk_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);
|
||||
|
||||
/* SYS PLL2 fixed output */
|
||||
clks[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);
|
||||
clks[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);
|
||||
clks[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);
|
||||
clks[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);
|
||||
clks[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);
|
||||
clks[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);
|
||||
clks[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);
|
||||
clks[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);
|
||||
clks[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);
|
||||
|
||||
clks[IMX8MQ_SYS2_PLL_50M] = imx_clk_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);
|
||||
clks[IMX8MQ_SYS2_PLL_100M] = imx_clk_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);
|
||||
clks[IMX8MQ_SYS2_PLL_125M] = imx_clk_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);
|
||||
clks[IMX8MQ_SYS2_PLL_166M] = imx_clk_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);
|
||||
clks[IMX8MQ_SYS2_PLL_200M] = imx_clk_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);
|
||||
clks[IMX8MQ_SYS2_PLL_250M] = imx_clk_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);
|
||||
clks[IMX8MQ_SYS2_PLL_333M] = imx_clk_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);
|
||||
clks[IMX8MQ_SYS2_PLL_500M] = imx_clk_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);
|
||||
clks[IMX8MQ_SYS2_PLL_1000M] = imx_clk_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
|
|
|
|||
|
|
@ -41,6 +41,38 @@ struct clk_pll14xx {
|
|||
|
||||
#define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
|
||||
PLL_1416X_RATE(1800000000U, 225, 3, 0),
|
||||
PLL_1416X_RATE(1600000000U, 200, 3, 0),
|
||||
PLL_1416X_RATE(1500000000U, 375, 3, 1),
|
||||
PLL_1416X_RATE(1400000000U, 350, 3, 1),
|
||||
PLL_1416X_RATE(1200000000U, 300, 3, 1),
|
||||
PLL_1416X_RATE(1000000000U, 250, 3, 1),
|
||||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
|
||||
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
|
||||
PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
|
||||
PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
|
||||
PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
|
||||
};
|
||||
|
||||
struct imx_pll14xx_clk imx_1443x_pll = {
|
||||
.type = PLL_1443X,
|
||||
.rate_table = imx_pll1443x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
|
||||
};
|
||||
|
||||
struct imx_pll14xx_clk imx_1416x_pll = {
|
||||
.type = PLL_1416X,
|
||||
.rate_table = imx_pll1416x_tbl,
|
||||
.rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
|
||||
struct clk_pll14xx *pll, unsigned long rate)
|
||||
{
|
||||
|
|
@ -112,43 +144,17 @@ static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
|
|||
return fvco;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv;
|
||||
|
||||
old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
|
||||
old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div_ctl0, u32 pll_div_ctl1)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv, old_kdiv;
|
||||
|
||||
old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
|
||||
rate->kdiv != old_kdiv;
|
||||
}
|
||||
|
||||
static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
|
||||
u32 pll_div_ctl0, u32 pll_div_ctl1)
|
||||
{
|
||||
u32 old_mdiv, old_pdiv, old_kdiv;
|
||||
|
||||
old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
|
||||
old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
|
||||
old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
|
||||
|
||||
return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
|
||||
rate->kdiv != old_kdiv;
|
||||
}
|
||||
|
||||
static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
|
||||
{
|
||||
u32 val;
|
||||
|
|
@ -174,7 +180,7 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
|
||||
tmp = readl_relaxed(pll->base + 4);
|
||||
|
||||
if (!clk_pll1416x_mp_change(rate, tmp)) {
|
||||
if (!clk_pll14xx_mp_change(rate, tmp)) {
|
||||
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
|
||||
tmp |= rate->sdiv << SDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 4);
|
||||
|
|
@ -239,13 +245,15 @@ static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
}
|
||||
|
||||
tmp = readl_relaxed(pll->base + 4);
|
||||
div_val = readl_relaxed(pll->base + 8);
|
||||
|
||||
if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
|
||||
if (!clk_pll14xx_mp_change(rate, tmp)) {
|
||||
tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
|
||||
tmp |= rate->sdiv << SDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 4);
|
||||
|
||||
tmp = rate->kdiv << KDIV_SHIFT;
|
||||
writel_relaxed(tmp, pll->base + 8);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -50,6 +50,9 @@ struct imx_pll14xx_clk {
|
|||
int flags;
|
||||
};
|
||||
|
||||
extern struct imx_pll14xx_clk imx_1416x_pll;
|
||||
extern struct imx_pll14xx_clk imx_1443x_pll;
|
||||
|
||||
#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
|
||||
imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -50,6 +50,20 @@
|
|||
#define AUDIO_CLK_PDMIN_CTRL1 0x0B0
|
||||
#define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
|
||||
|
||||
/* SM1 introduce new register and some shifts :( */
|
||||
#define AUDIO_CLK_GATE_EN1 0x004
|
||||
#define AUDIO_SM1_MCLK_A_CTRL 0x008
|
||||
#define AUDIO_SM1_MCLK_B_CTRL 0x00C
|
||||
#define AUDIO_SM1_MCLK_C_CTRL 0x010
|
||||
#define AUDIO_SM1_MCLK_D_CTRL 0x014
|
||||
#define AUDIO_SM1_MCLK_E_CTRL 0x018
|
||||
#define AUDIO_SM1_MCLK_F_CTRL 0x01C
|
||||
#define AUDIO_SM1_MST_PAD_CTRL0 0x020
|
||||
#define AUDIO_SM1_MST_PAD_CTRL1 0x024
|
||||
#define AUDIO_SM1_SW_RESET0 0x028
|
||||
#define AUDIO_SM1_SW_RESET1 0x02C
|
||||
#define AUDIO_CLK81_CTRL 0x030
|
||||
#define AUDIO_CLK81_EN 0x034
|
||||
/*
|
||||
* CLKID index values
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
|
|
@ -115,10 +129,15 @@
|
|||
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
|
||||
#define AUD_CLKID_CLK81_EN 173
|
||||
#define AUD_CLKID_SYSCLK_A_DIV 174
|
||||
#define AUD_CLKID_SYSCLK_B_DIV 175
|
||||
#define AUD_CLKID_SYSCLK_A_EN 176
|
||||
#define AUD_CLKID_SYSCLK_B_EN 177
|
||||
|
||||
/* include the CLKIDs which are part of the DT bindings */
|
||||
#include <dt-bindings/clock/axg-audio-clkc.h>
|
||||
|
||||
#define NR_CLKS 163
|
||||
#define NR_CLKS 178
|
||||
|
||||
#endif /*__AXG_AUDIO_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -343,6 +343,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
|
|||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x3,
|
||||
.shift = 0,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn0_sel",
|
||||
|
|
@ -353,8 +354,7 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
|
|||
{ .hw = &g12a_fclk_div3.hw },
|
||||
},
|
||||
.num_parents = 3,
|
||||
/* This sub-tree is used a parking clock */
|
||||
.flags = CLK_SET_RATE_NO_REPARENT,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -410,6 +410,7 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
|
|||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 2,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn0",
|
||||
|
|
@ -466,6 +467,7 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
|
|||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 10,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk_dyn",
|
||||
|
|
@ -485,6 +487,7 @@ static struct clk_regmap g12a_cpu_clk = {
|
|||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk",
|
||||
|
|
@ -504,6 +507,7 @@ static struct clk_regmap g12b_cpu_clk = {
|
|||
.offset = HHI_SYS_CPU_CLK_CNTL0,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpu_clk",
|
||||
|
|
@ -523,6 +527,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
|
|||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x3,
|
||||
.shift = 0,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn0_sel",
|
||||
|
|
@ -533,6 +538,7 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
|
|||
{ .hw = &g12a_fclk_div3.hw },
|
||||
},
|
||||
.num_parents = 3,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -567,6 +573,7 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
|
|||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 2,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn0",
|
||||
|
|
@ -644,6 +651,7 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
|
|||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 10,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk_dyn",
|
||||
|
|
@ -663,6 +671,7 @@ static struct clk_regmap g12b_cpub_clk = {
|
|||
.offset = HHI_SYS_CPUB_CLK_CNTL,
|
||||
.mask = 0x1,
|
||||
.shift = 11,
|
||||
.flags = CLK_MUX_ROUND_CLOSEST,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "cpub_clk",
|
||||
|
|
|
|||
|
|
@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
|
|||
&gxbb_sar_adc_clk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@ config CLK_RENESAS
|
|||
select CLK_R8A7745 if ARCH_R8A7745
|
||||
select CLK_R8A77470 if ARCH_R8A77470
|
||||
select CLK_R8A774A1 if ARCH_R8A774A1
|
||||
select CLK_R8A774B1 if ARCH_R8A774B1
|
||||
select CLK_R8A774C0 if ARCH_R8A774C0
|
||||
select CLK_R8A7778 if ARCH_R8A7778
|
||||
select CLK_R8A7779 if ARCH_R8A7779
|
||||
|
|
@ -20,7 +21,8 @@ config CLK_RENESAS
|
|||
select CLK_R8A7792 if ARCH_R8A7792
|
||||
select CLK_R8A7794 if ARCH_R8A7794
|
||||
select CLK_R8A7795 if ARCH_R8A7795
|
||||
select CLK_R8A7796 if ARCH_R8A7796
|
||||
select CLK_R8A77960 if ARCH_R8A77960 || ARCH_R8A7796
|
||||
select CLK_R8A77961 if ARCH_R8A77961
|
||||
select CLK_R8A77965 if ARCH_R8A77965
|
||||
select CLK_R8A77970 if ARCH_R8A77970
|
||||
select CLK_R8A77980 if ARCH_R8A77980
|
||||
|
|
@ -31,17 +33,6 @@ config CLK_RENESAS
|
|||
|
||||
if CLK_RENESAS
|
||||
|
||||
config CLK_RENESAS_LEGACY
|
||||
bool "Legacy DT clock support"
|
||||
depends on CLK_R8A7790 || CLK_R8A7791 || CLK_R8A7792 || CLK_R8A7794
|
||||
help
|
||||
Enable backward compatibility with old device trees describing a
|
||||
hierarchical representation of the various CPG and MSTP clocks.
|
||||
|
||||
Say Y if you want your kernel to work with old DTBs.
|
||||
It is safe to say N if you use the DTS that is supplied with the
|
||||
current kernel source tree.
|
||||
|
||||
# SoC
|
||||
config CLK_EMEV2
|
||||
bool "Emma Mobile EV2 clock support" if COMPILE_TEST
|
||||
|
|
@ -80,6 +71,10 @@ config CLK_R8A774A1
|
|||
bool "RZ/G2M clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A774B1
|
||||
bool "RZ/G2N clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A774C0
|
||||
bool "RZ/G2E clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
|
@ -94,24 +89,20 @@ config CLK_R8A7779
|
|||
|
||||
config CLK_R8A7790
|
||||
bool "R-Car H2 clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7791
|
||||
bool "R-Car M2-W/N clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_R8A7792
|
||||
bool "R-Car V2H clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
|
||||
config CLK_R8A7794
|
||||
bool "R-Car E2 clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN2 if CLK_RENESAS_LEGACY
|
||||
select CLK_RCAR_GEN2_CPG
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
|
|
@ -119,10 +110,14 @@ config CLK_R8A7795
|
|||
bool "R-Car H3 clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A7796
|
||||
config CLK_R8A77960
|
||||
bool "R-Car M3-W clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A77961
|
||||
bool "R-Car M3-W+ clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
||||
config CLK_R8A77965
|
||||
bool "R-Car M3-N clock support" if COMPILE_TEST
|
||||
select CLK_RCAR_GEN3_CPG
|
||||
|
|
@ -155,11 +150,6 @@ config CLK_SH73A0
|
|||
|
||||
|
||||
# Family
|
||||
config CLK_RCAR_GEN2
|
||||
bool "R-Car Gen2 legacy clock support" if COMPILE_TEST
|
||||
select CLK_RENESAS_CPG_MSTP
|
||||
select CLK_RENESAS_DIV6
|
||||
|
||||
config CLK_RCAR_GEN2_CPG
|
||||
bool "R-Car Gen2 CPG clock support" if COMPILE_TEST
|
||||
select CLK_RENESAS_CPG_MSSR
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@ obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
|
|||
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77470) += r8a77470-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A774C0) += r8a774c0-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
|
||||
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
|
||||
|
|
@ -17,7 +18,8 @@ obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
|
|||
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
|
||||
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
|
||||
|
|
@ -27,7 +29,6 @@ obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
|
|||
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
|
||||
|
||||
# Family
|
||||
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
|
||||
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
|
||||
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
|
||||
|
|
|
|||
|
|
@ -189,10 +189,8 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
|
|||
unsigned int i;
|
||||
|
||||
group = kzalloc(struct_size(group, clks, MSTP_MAX_CLOCKS), GFP_KERNEL);
|
||||
if (group == NULL) {
|
||||
kfree(group);
|
||||
if (!group)
|
||||
return;
|
||||
}
|
||||
|
||||
clks = group->clks;
|
||||
spin_lock_init(&group->lock);
|
||||
|
|
|
|||
|
|
@ -1,457 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rcar_gen2 Core CPG Clocks
|
||||
*
|
||||
* Copyright (C) 2013 Ideas On Board SPRL
|
||||
*
|
||||
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/math64.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
struct rcar_gen2_cpg {
|
||||
struct clk_onecell_data data;
|
||||
spinlock_t lock;
|
||||
void __iomem *reg;
|
||||
};
|
||||
|
||||
#define CPG_FRQCRB 0x00000004
|
||||
#define CPG_FRQCRB_KICK BIT(31)
|
||||
#define CPG_SDCKCR 0x00000074
|
||||
#define CPG_PLL0CR 0x000000d8
|
||||
#define CPG_FRQCRC 0x000000e0
|
||||
#define CPG_FRQCRC_ZFC_MASK (0x1f << 8)
|
||||
#define CPG_FRQCRC_ZFC_SHIFT 8
|
||||
#define CPG_ADSPCKCR 0x0000025c
|
||||
#define CPG_RCANCKCR 0x00000270
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Z Clock
|
||||
*
|
||||
* Traits of this clock:
|
||||
* prepare - clk_prepare only ensures that parents are prepared
|
||||
* enable - clk_enable only ensures that parents are enabled
|
||||
* rate - rate is adjustable. clk->rate = parent->rate * mult / 32
|
||||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
struct cpg_z_clk {
|
||||
struct clk_hw hw;
|
||||
void __iomem *reg;
|
||||
void __iomem *kick_reg;
|
||||
};
|
||||
|
||||
#define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw)
|
||||
|
||||
static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
unsigned int val;
|
||||
|
||||
val = (readl(zclk->reg) & CPG_FRQCRC_ZFC_MASK) >> CPG_FRQCRC_ZFC_SHIFT;
|
||||
mult = 32 - val;
|
||||
|
||||
return div_u64((u64)parent_rate * mult, 32);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
unsigned long prate = *parent_rate;
|
||||
unsigned int mult;
|
||||
|
||||
if (!prate)
|
||||
prate = 1;
|
||||
|
||||
mult = div_u64((u64)rate * 32, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
return *parent_rate / 32 * mult;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int mult;
|
||||
u32 val, kick;
|
||||
unsigned int i;
|
||||
|
||||
mult = div_u64((u64)rate * 32, parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
return -EBUSY;
|
||||
|
||||
val = readl(zclk->reg);
|
||||
val &= ~CPG_FRQCRC_ZFC_MASK;
|
||||
val |= (32 - mult) << CPG_FRQCRC_ZFC_SHIFT;
|
||||
writel(val, zclk->reg);
|
||||
|
||||
/*
|
||||
* Set KICK bit in FRQCRB to update hardware setting and wait for
|
||||
* clock change completion.
|
||||
*/
|
||||
kick = readl(zclk->kick_reg);
|
||||
kick |= CPG_FRQCRB_KICK;
|
||||
writel(kick, zclk->kick_reg);
|
||||
|
||||
/*
|
||||
* Note: There is no HW information about the worst case latency.
|
||||
*
|
||||
* Using experimental measurements, it seems that no more than
|
||||
* ~10 iterations are needed, independently of the CPU rate.
|
||||
* Since this value might be dependent on external xtal rate, pll1
|
||||
* rate or even the other emulation clocks rate, use 1000 as a
|
||||
* "super" safe value.
|
||||
*/
|
||||
for (i = 1000; i; i--) {
|
||||
if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK))
|
||||
return 0;
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_z_clk_register(struct rcar_gen2_cpg *cpg)
|
||||
{
|
||||
static const char *parent_name = "pll0";
|
||||
struct clk_init_data init;
|
||||
struct cpg_z_clk *zclk;
|
||||
struct clk *clk;
|
||||
|
||||
zclk = kzalloc(sizeof(*zclk), GFP_KERNEL);
|
||||
if (!zclk)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = "z";
|
||||
init.ops = &cpg_z_clk_ops;
|
||||
init.flags = 0;
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
zclk->reg = cpg->reg + CPG_FRQCRC;
|
||||
zclk->kick_reg = cpg->reg + CPG_FRQCRB;
|
||||
zclk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &zclk->hw);
|
||||
if (IS_ERR(clk))
|
||||
kfree(zclk);
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
static struct clk * __init cpg_rcan_clk_register(struct rcar_gen2_cpg *cpg,
|
||||
struct device_node *np)
|
||||
{
|
||||
const char *parent_name = of_clk_get_parent_name(np, 1);
|
||||
struct clk_fixed_factor *fixed;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
|
||||
if (!fixed)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
fixed->mult = 1;
|
||||
fixed->div = 6;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(fixed);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = cpg->reg + CPG_RCANCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg->lock;
|
||||
|
||||
clk = clk_register_composite(NULL, "rcan", &parent_name, 1, NULL, NULL,
|
||||
&fixed->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(fixed);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* ADSP divisors */
|
||||
static const struct clk_div_table cpg_adsp_div_table[] = {
|
||||
{ 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 },
|
||||
{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
|
||||
{ 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static struct clk * __init cpg_adsp_clk_register(struct rcar_gen2_cpg *cpg)
|
||||
{
|
||||
const char *parent_name = "pll1";
|
||||
struct clk_divider *div;
|
||||
struct clk_gate *gate;
|
||||
struct clk *clk;
|
||||
|
||||
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
||||
if (!div)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
div->reg = cpg->reg + CPG_ADSPCKCR;
|
||||
div->width = 4;
|
||||
div->table = cpg_adsp_div_table;
|
||||
div->lock = &cpg->lock;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate) {
|
||||
kfree(div);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
gate->reg = cpg->reg + CPG_ADSPCKCR;
|
||||
gate->bit_idx = 8;
|
||||
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
||||
gate->lock = &cpg->lock;
|
||||
|
||||
clk = clk_register_composite(NULL, "adsp", &parent_name, 1, NULL, NULL,
|
||||
&div->hw, &clk_divider_ops,
|
||||
&gate->hw, &clk_gate_ops, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(div);
|
||||
}
|
||||
|
||||
return clk;
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3
|
||||
* 14 13 19 (MHz) *1 *1
|
||||
*---------------------------------------------------
|
||||
* 0 0 0 15 x 1 x172/2 x208/2 x106
|
||||
* 0 0 1 15 x 1 x172/2 x208/2 x88
|
||||
* 0 1 0 20 x 1 x130/2 x156/2 x80
|
||||
* 0 1 1 20 x 1 x130/2 x156/2 x66
|
||||
* 1 0 0 26 / 2 x200/2 x240/2 x122
|
||||
* 1 0 1 26 / 2 x200/2 x240/2 x102
|
||||
* 1 1 0 30 / 2 x172/2 x208/2 x106
|
||||
* 1 1 1 30 / 2 x172/2 x208/2 x88
|
||||
*
|
||||
* *1 : Table 7.6 indicates VCO output (PLLx = VCO/2)
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
|
||||
(((md) & BIT(13)) >> 12) | \
|
||||
(((md) & BIT(19)) >> 19))
|
||||
struct cpg_pll_config {
|
||||
unsigned int extal_div;
|
||||
unsigned int pll1_mult;
|
||||
unsigned int pll3_mult;
|
||||
unsigned int pll0_mult; /* For R-Car V2H and E2 only */
|
||||
};
|
||||
|
||||
static const struct cpg_pll_config cpg_pll_configs[8] __initconst = {
|
||||
{ 1, 208, 106, 200 }, { 1, 208, 88, 200 },
|
||||
{ 1, 156, 80, 150 }, { 1, 156, 66, 150 },
|
||||
{ 2, 240, 122, 230 }, { 2, 240, 102, 230 },
|
||||
{ 2, 208, 106, 200 }, { 2, 208, 88, 200 },
|
||||
};
|
||||
|
||||
/* SDHI divisors */
|
||||
static const struct clk_div_table cpg_sdh_div_table[] = {
|
||||
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
|
||||
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
|
||||
{ 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table cpg_sd01_div_table[] = {
|
||||
{ 4, 8 },
|
||||
{ 5, 12 }, { 6, 16 }, { 7, 18 }, { 8, 24 },
|
||||
{ 10, 36 }, { 11, 48 }, { 12, 10 }, { 0, 0 },
|
||||
};
|
||||
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Initialization
|
||||
*/
|
||||
|
||||
static u32 cpg_mode __initdata;
|
||||
|
||||
static const char * const pll0_mult_match[] = {
|
||||
"renesas,r8a7792-cpg-clocks",
|
||||
"renesas,r8a7794-cpg-clocks",
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
|
||||
const struct cpg_pll_config *config,
|
||||
const char *name)
|
||||
{
|
||||
const struct clk_div_table *table = NULL;
|
||||
const char *parent_name;
|
||||
unsigned int shift;
|
||||
unsigned int mult = 1;
|
||||
unsigned int div = 1;
|
||||
|
||||
if (!strcmp(name, "main")) {
|
||||
parent_name = of_clk_get_parent_name(np, 0);
|
||||
div = config->extal_div;
|
||||
} else if (!strcmp(name, "pll0")) {
|
||||
/* PLL0 is a configurable multiplier clock. Register it as a
|
||||
* fixed factor clock for now as there's no generic multiplier
|
||||
* clock implementation and we currently have no need to change
|
||||
* the multiplier value.
|
||||
*/
|
||||
if (of_device_compatible_match(np, pll0_mult_match)) {
|
||||
/* R-Car V2H and E2 do not have PLL0CR */
|
||||
mult = config->pll0_mult;
|
||||
div = 3;
|
||||
} else {
|
||||
u32 value = readl(cpg->reg + CPG_PLL0CR);
|
||||
mult = ((value >> 24) & ((1 << 7) - 1)) + 1;
|
||||
}
|
||||
parent_name = "main";
|
||||
} else if (!strcmp(name, "pll1")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll1_mult / 2;
|
||||
} else if (!strcmp(name, "pll3")) {
|
||||
parent_name = "main";
|
||||
mult = config->pll3_mult;
|
||||
} else if (!strcmp(name, "lb")) {
|
||||
parent_name = "pll1";
|
||||
div = cpg_mode & BIT(18) ? 36 : 24;
|
||||
} else if (!strcmp(name, "qspi")) {
|
||||
parent_name = "pll1_div2";
|
||||
div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
|
||||
? 8 : 10;
|
||||
} else if (!strcmp(name, "sdh")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sdh_div_table;
|
||||
shift = 8;
|
||||
} else if (!strcmp(name, "sd0")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 4;
|
||||
} else if (!strcmp(name, "sd1")) {
|
||||
parent_name = "pll1";
|
||||
table = cpg_sd01_div_table;
|
||||
shift = 0;
|
||||
} else if (!strcmp(name, "z")) {
|
||||
return cpg_z_clk_register(cpg);
|
||||
} else if (!strcmp(name, "rcan")) {
|
||||
return cpg_rcan_clk_register(cpg, np);
|
||||
} else if (!strcmp(name, "adsp")) {
|
||||
return cpg_adsp_clk_register(cpg);
|
||||
} else {
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
if (!table)
|
||||
return clk_register_fixed_factor(NULL, name, parent_name, 0,
|
||||
mult, div);
|
||||
else
|
||||
return clk_register_divider_table(NULL, name, parent_name, 0,
|
||||
cpg->reg + CPG_SDCKCR, shift,
|
||||
4, 0, table, &cpg->lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset register definitions.
|
||||
*/
|
||||
#define MODEMR 0xe6160060
|
||||
|
||||
static u32 __init rcar_gen2_read_mode_pins(void)
|
||||
{
|
||||
void __iomem *modemr = ioremap_nocache(MODEMR, 4);
|
||||
u32 mode;
|
||||
|
||||
BUG_ON(!modemr);
|
||||
mode = ioread32(modemr);
|
||||
iounmap(modemr);
|
||||
|
||||
return mode;
|
||||
}
|
||||
|
||||
static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
|
||||
{
|
||||
const struct cpg_pll_config *config;
|
||||
struct rcar_gen2_cpg *cpg;
|
||||
struct clk **clks;
|
||||
unsigned int i;
|
||||
int num_clks;
|
||||
|
||||
if (rcar_rst_read_mode_pins(&cpg_mode)) {
|
||||
/* Backward-compatibility with old DT */
|
||||
pr_warn("%pOF: failed to obtain mode pins from RST\n", np);
|
||||
cpg_mode = rcar_gen2_read_mode_pins();
|
||||
}
|
||||
|
||||
num_clks = of_property_count_strings(np, "clock-output-names");
|
||||
if (num_clks < 0) {
|
||||
pr_err("%s: failed to count clocks\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
|
||||
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
|
||||
if (cpg == NULL || clks == NULL) {
|
||||
/* We're leaking memory on purpose, there's no point in cleaning
|
||||
* up as the system won't boot anyway.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
spin_lock_init(&cpg->lock);
|
||||
|
||||
cpg->data.clks = clks;
|
||||
cpg->data.clk_num = num_clks;
|
||||
|
||||
cpg->reg = of_iomap(np, 0);
|
||||
if (WARN_ON(cpg->reg == NULL))
|
||||
return;
|
||||
|
||||
config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
|
||||
for (i = 0; i < num_clks; ++i) {
|
||||
const char *name;
|
||||
struct clk *clk;
|
||||
|
||||
of_property_read_string_index(np, "clock-output-names", i,
|
||||
&name);
|
||||
|
||||
clk = rcar_gen2_cpg_register_clock(np, cpg, config, name);
|
||||
if (IS_ERR(clk))
|
||||
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
|
||||
__func__, np, name, PTR_ERR(clk));
|
||||
else
|
||||
cpg->data.clks[i] = clk;
|
||||
}
|
||||
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
|
||||
|
||||
cpg_mstp_add_clk_domain(np);
|
||||
}
|
||||
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
|
||||
rcar_gen2_cpg_clocks_init);
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7796-cpg-mssr.c
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
|
||||
|
||||
#include "renesas-cpg-mssr.h"
|
||||
#include "rcar-gen3-cpg.h"
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
|
||||
|
||||
/* External Input Clocks */
|
||||
CLK_EXTAL,
|
||||
CLK_EXTALR,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_MAIN,
|
||||
CLK_PLL0,
|
||||
CLK_PLL1,
|
||||
CLK_PLL3,
|
||||
CLK_PLL4,
|
||||
CLK_PLL1_DIV2,
|
||||
CLK_PLL1_DIV4,
|
||||
CLK_S0,
|
||||
CLK_S1,
|
||||
CLK_S2,
|
||||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE
|
||||
};
|
||||
|
||||
static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
DEF_INPUT("extalr", CLK_EXTALR),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
|
||||
DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
|
||||
DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
|
||||
DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
|
||||
DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
|
||||
|
||||
DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
|
||||
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
|
||||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
/* Core Clock Outputs */
|
||||
DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
|
||||
DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
|
||||
DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
|
||||
DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
|
||||
DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
|
||||
DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
|
||||
DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
|
||||
DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
|
||||
DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
|
||||
DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
|
||||
DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
|
||||
DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
|
||||
DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
|
||||
DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
|
||||
DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
|
||||
DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
|
||||
DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
|
||||
DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
|
||||
DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
|
||||
DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
|
||||
DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
|
||||
DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
|
||||
|
||||
DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
|
||||
|
||||
DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
|
||||
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
|
||||
DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
|
||||
DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
|
||||
DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
|
||||
DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
|
||||
DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
|
||||
DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
|
||||
DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
|
||||
DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
|
||||
DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
|
||||
DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
|
||||
DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
|
||||
DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
|
||||
DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
|
||||
DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
|
||||
DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
|
||||
DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
|
||||
DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
|
||||
DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
|
||||
DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
|
||||
DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
|
||||
DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
|
||||
DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
|
||||
DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
|
||||
DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
|
||||
DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
|
||||
DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
|
||||
DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
|
||||
DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
|
||||
DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
|
||||
};
|
||||
|
||||
static const unsigned int r8a774b1_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_ID(408), /* INTC-AP (GIC) */
|
||||
};
|
||||
|
||||
/*
|
||||
* CPG Clock Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
|
||||
* 14 13 19 17 (MHz)
|
||||
*-----------------------------------------------------------------
|
||||
* 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
|
||||
* 0 0 1 0 Prohibited setting
|
||||
* 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
|
||||
* 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
|
||||
* 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
|
||||
* 0 1 1 0 Prohibited setting
|
||||
* 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
|
||||
* 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
|
||||
* 1 0 1 0 Prohibited setting
|
||||
* 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
|
||||
* 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
|
||||
* 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
|
||||
* 1 1 1 0 Prohibited setting
|
||||
* 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
|
||||
*/
|
||||
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
|
||||
(((md) & BIT(13)) >> 11) | \
|
||||
(((md) & BIT(19)) >> 18) | \
|
||||
(((md) & BIT(17)) >> 17))
|
||||
|
||||
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
||||
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 192, 1, 128, 1, 16, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 192, 1, 192, 1, 16, },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 160, 1, 106, 1, 19, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 160, 1, 160, 1, 19, },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 1, 128, 1, 84, 1, 24, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 1, 128, 1, 128, 1, 24, },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
{ 2, 192, 1, 128, 1, 32, },
|
||||
{ 0, /* Prohibited setting */ },
|
||||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
static int __init r8a774b1_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
u32 cpg_mode;
|
||||
int error;
|
||||
|
||||
error = rcar_rst_read_mode_pins(&cpg_mode);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
|
||||
if (!cpg_pll_config->extal_div) {
|
||||
dev_err(dev, "Prohibited setting (cpg_mode=0x%x)\n", cpg_mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a774b1_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r8a774b1_core_clks,
|
||||
.num_core_clks = ARRAY_SIZE(r8a774b1_core_clks),
|
||||
.last_dt_core_clk = LAST_DT_CORE_CLK,
|
||||
.num_total_core_clks = MOD_CLK_BASE,
|
||||
|
||||
/* Module Clocks */
|
||||
.mod_clks = r8a774b1_mod_clks,
|
||||
.num_mod_clks = ARRAY_SIZE(r8a774b1_mod_clks),
|
||||
.num_hw_mod_clks = 12 * 32,
|
||||
|
||||
/* Critical Module Clocks */
|
||||
.crit_mod_clks = r8a774b1_crit_mod_clks,
|
||||
.num_crit_mod_clks = ARRAY_SIZE(r8a774b1_crit_mod_clks),
|
||||
|
||||
/* Callbacks */
|
||||
.init = r8a774b1_cpg_mssr_init,
|
||||
.cpg_clk_register = rcar_gen3_cpg_clk_register,
|
||||
};
|
||||
|
|
@ -1,9 +1,10 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
|
||||
* r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
|
||||
* Reset
|
||||
*
|
||||
* Copyright (C) 2016 Glider bvba
|
||||
* Copyright (C) 2018 Renesas Electronics Corp.
|
||||
* Copyright (C) 2016-2019 Glider bvba
|
||||
* Copyright (C) 2018-2019 Renesas Electronics Corp.
|
||||
*
|
||||
* Based on r8a7795-cpg-mssr.c
|
||||
*
|
||||
|
|
@ -14,6 +15,7 @@
|
|||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/soc/renesas/rcar-rst.h>
|
||||
|
||||
#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
|
||||
|
|
@ -116,7 +118,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
|
||||
};
|
||||
|
||||
static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
|
||||
static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
|
||||
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
|
||||
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
|
||||
|
|
@ -304,6 +306,14 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
|
|||
{ 2, 192, 1, 192, 1, 32, },
|
||||
};
|
||||
|
||||
/*
|
||||
* Fixups for R-Car M3-W+
|
||||
*/
|
||||
|
||||
static const unsigned int r8a77961_mod_nullify[] __initconst = {
|
||||
MOD_CLK_ID(617), /* FCPCI0 */
|
||||
};
|
||||
|
||||
static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
||||
{
|
||||
const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
|
||||
|
|
@ -320,6 +330,12 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(dev->of_node, "renesas,r8a77961-cpg-mssr"))
|
||||
mssr_mod_nullify(r8a7796_mod_clks,
|
||||
ARRAY_SIZE(r8a7796_mod_clks),
|
||||
r8a77961_mod_nullify,
|
||||
ARRAY_SIZE(r8a77961_mod_nullify));
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -323,7 +323,7 @@ static int __init r8a77965_cpg_mssr_init(struct device *dev)
|
|||
}
|
||||
|
||||
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
|
||||
};
|
||||
}
|
||||
|
||||
const struct cpg_mssr_info r8a77965_cpg_mssr_info __initconst = {
|
||||
/* Core Clocks */
|
||||
|
|
|
|||
|
|
@ -63,19 +63,22 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
|||
return div_u64((u64)parent_rate * mult, 32);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long prate = *parent_rate;
|
||||
unsigned int mult;
|
||||
unsigned long prate = req->best_parent_rate;
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
|
||||
if (!prate)
|
||||
prate = 1;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
mult = div_u64((u64)rate * 32, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
mult = div64_ul(req->rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
return *parent_rate / 32 * mult;
|
||||
req->rate = div_u64((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -86,7 +89,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
u32 val, kick;
|
||||
unsigned int i;
|
||||
|
||||
mult = div_u64((u64)rate * 32, parent_rate);
|
||||
mult = div64_ul(rate * 32ULL, parent_rate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
|
||||
if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK)
|
||||
|
|
@ -126,7 +129,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.determine_rate = cpg_z_clk_determine_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -114,18 +114,24 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
|
|||
32 * zclk->fixed_div);
|
||||
}
|
||||
|
||||
static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
static int cpg_z_clk_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct cpg_z_clk *zclk = to_z_clk(hw);
|
||||
unsigned int min_mult, max_mult, mult;
|
||||
unsigned long prate;
|
||||
unsigned int mult;
|
||||
|
||||
prate = *parent_rate / zclk->fixed_div;
|
||||
mult = div_u64(rate * 32ULL, prate);
|
||||
mult = clamp(mult, 1U, 32U);
|
||||
prate = req->best_parent_rate / zclk->fixed_div;
|
||||
min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL);
|
||||
max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL);
|
||||
if (max_mult < min_mult)
|
||||
return -EINVAL;
|
||||
|
||||
return (u64)prate * mult / 32;
|
||||
mult = div64_ul(req->rate * 32ULL, prate);
|
||||
mult = clamp(mult, min_mult, max_mult);
|
||||
|
||||
req->rate = div_u64((u64)prate * mult, 32);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
|
@ -172,7 +178,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops cpg_z_clk_ops = {
|
||||
.recalc_rate = cpg_z_clk_recalc_rate,
|
||||
.round_rate = cpg_z_clk_round_rate,
|
||||
.determine_rate = cpg_z_clk_determine_rate,
|
||||
.set_rate = cpg_z_clk_set_rate,
|
||||
};
|
||||
|
||||
|
|
@ -309,44 +315,44 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
|
|||
clock->div_table[clock->cur_div_idx].div);
|
||||
}
|
||||
|
||||
static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
static int cpg_sd_clock_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
unsigned long calc_rate, diff, diff_min = ULONG_MAX;
|
||||
unsigned int i, best_div = 0;
|
||||
unsigned long best_rate = ULONG_MAX, diff_min = ULONG_MAX;
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned long calc_rate, diff;
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < clock->div_num; i++) {
|
||||
calc_rate = DIV_ROUND_CLOSEST(parent_rate,
|
||||
calc_rate = DIV_ROUND_CLOSEST(req->best_parent_rate,
|
||||
clock->div_table[i].div);
|
||||
diff = calc_rate > rate ? calc_rate - rate : rate - calc_rate;
|
||||
if (calc_rate < req->min_rate || calc_rate > req->max_rate)
|
||||
continue;
|
||||
|
||||
diff = calc_rate > req->rate ? calc_rate - req->rate
|
||||
: req->rate - calc_rate;
|
||||
if (diff < diff_min) {
|
||||
best_div = clock->div_table[i].div;
|
||||
best_rate = calc_rate;
|
||||
diff_min = diff;
|
||||
}
|
||||
}
|
||||
|
||||
return best_div;
|
||||
}
|
||||
if (best_rate == ULONG_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
|
||||
|
||||
return DIV_ROUND_CLOSEST(*parent_rate, div);
|
||||
req->rate = best_rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct sd_clock *clock = to_sd_clock(hw);
|
||||
unsigned int div = cpg_sd_clock_calc_div(clock, rate, parent_rate);
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < clock->div_num; i++)
|
||||
if (div == clock->div_table[i].div)
|
||||
if (rate == DIV_ROUND_CLOSEST(parent_rate,
|
||||
clock->div_table[i].div))
|
||||
break;
|
||||
|
||||
if (i >= clock->div_num)
|
||||
|
|
@ -366,7 +372,7 @@ static const struct clk_ops cpg_sd_clock_ops = {
|
|||
.disable = cpg_sd_clock_disable,
|
||||
.is_enabled = cpg_sd_clock_is_enabled,
|
||||
.recalc_rate = cpg_sd_clock_recalc_rate,
|
||||
.round_rate = cpg_sd_clock_round_rate,
|
||||
.determine_rate = cpg_sd_clock_determine_rate,
|
||||
.set_rate = cpg_sd_clock_set_rate,
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -702,6 +702,12 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a774a1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774B1
|
||||
{
|
||||
.compatible = "renesas,r8a774b1-cpg-mssr",
|
||||
.data = &r8a774b1_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A774C0
|
||||
{
|
||||
.compatible = "renesas,r8a774c0-cpg-mssr",
|
||||
|
|
@ -743,12 +749,18 @@ static const struct of_device_id cpg_mssr_match[] = {
|
|||
.data = &r8a7795_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A7796
|
||||
#ifdef CONFIG_CLK_R8A77960
|
||||
{
|
||||
.compatible = "renesas,r8a7796-cpg-mssr",
|
||||
.data = &r8a7796_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77961
|
||||
{
|
||||
.compatible = "renesas,r8a77961-cpg-mssr",
|
||||
.data = &r8a7796_cpg_mssr_info,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_CLK_R8A77965
|
||||
{
|
||||
.compatible = "renesas,r8a77965-cpg-mssr",
|
||||
|
|
|
|||
|
|
@ -159,6 +159,7 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
|
|||
extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a77470_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774a1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774b1_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a774c0_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7790_cpg_mssr_info;
|
||||
extern const struct cpg_mssr_info r8a7791_cpg_mssr_info;
|
||||
|
|
|
|||
|
|
@ -165,12 +165,20 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
|
|||
GATE_BUS_CPU,
|
||||
GATE_SCLK_CPU,
|
||||
CLKOUT_CMU_CPU,
|
||||
APLL_CON0,
|
||||
KPLL_CON0,
|
||||
CPLL_CON0,
|
||||
DPLL_CON0,
|
||||
EPLL_CON0,
|
||||
EPLL_CON1,
|
||||
EPLL_CON2,
|
||||
RPLL_CON0,
|
||||
RPLL_CON1,
|
||||
RPLL_CON2,
|
||||
IPLL_CON0,
|
||||
SPLL_CON0,
|
||||
VPLL_CON0,
|
||||
MPLL_CON0,
|
||||
SRC_TOP0,
|
||||
SRC_TOP1,
|
||||
SRC_TOP2,
|
||||
|
|
@ -605,7 +613,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
|||
MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
|
||||
MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
|
||||
|
||||
MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
|
||||
MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
|
||||
SRC_TOP3, 0, 1),
|
||||
|
|
@ -647,8 +656,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
|||
SRC_TOP5, 8, 1),
|
||||
MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
|
||||
SRC_TOP5, 12, 1),
|
||||
MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
|
||||
SRC_TOP5, 16, 1),
|
||||
MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
|
||||
SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
|
||||
SRC_TOP5, 20, 1),
|
||||
MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
|
||||
|
|
@ -657,7 +666,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
|||
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
|
||||
|
||||
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
|
||||
MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
|
||||
MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
|
||||
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
|
||||
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
|
||||
|
|
@ -701,7 +711,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
|
|||
SRC_TOP12, 8, 1),
|
||||
MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
|
||||
SRC_TOP12, 12, 1),
|
||||
MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
|
||||
MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
|
||||
SRC_TOP12, 20, 1),
|
||||
MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
|
||||
|
|
@ -798,8 +809,8 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
|
|||
DIV_TOP2, 8, 3),
|
||||
DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
|
||||
DIV_TOP2, 12, 3),
|
||||
DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
|
||||
16, 3),
|
||||
DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
|
||||
16, 3, CLK_SET_RATE_PARENT, 0),
|
||||
DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
|
||||
DIV_TOP2, 20, 3),
|
||||
DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
|
||||
|
|
@ -1172,8 +1183,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
|
|||
GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
|
||||
GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
|
||||
|
||||
/* CDREX */
|
||||
GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
|
||||
GATE_BUS_CDREX0, 0, 0, 0),
|
||||
|
|
@ -1248,6 +1257,16 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
|
|||
{ DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
|
||||
};
|
||||
|
||||
static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
|
||||
GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
|
||||
CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
|
||||
{ GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
|
||||
{ SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
|
||||
};
|
||||
|
||||
static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
|
||||
DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
|
||||
};
|
||||
|
|
@ -1320,6 +1339,14 @@ static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
|
|||
.pd_name = "GSC",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
|
||||
.gate_clks = exynos5x_g3d_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
|
||||
.suspend_regs = exynos5x_g3d_suspend_regs,
|
||||
.nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
|
||||
.pd_name = "G3D",
|
||||
};
|
||||
|
||||
static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
|
||||
.div_clks = exynos5x_mfc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
|
||||
|
|
@ -1351,6 +1378,7 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
|
|||
static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
|
||||
&exynos5x_disp_subcmu,
|
||||
&exynos5x_gsc_subcmu,
|
||||
&exynos5x_g3d_subcmu,
|
||||
&exynos5x_mfc_subcmu,
|
||||
&exynos5x_mscl_subcmu,
|
||||
};
|
||||
|
|
@ -1358,6 +1386,7 @@ static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
|
|||
static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
|
||||
&exynos5x_disp_subcmu,
|
||||
&exynos5x_gsc_subcmu,
|
||||
&exynos5x_g3d_subcmu,
|
||||
&exynos5x_mfc_subcmu,
|
||||
&exynos5x_mscl_subcmu,
|
||||
&exynos5800_mau_subcmu,
|
||||
|
|
@ -1414,6 +1443,17 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
|
|||
PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
|
||||
};
|
||||
|
||||
static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
|
||||
PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
|
||||
PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
|
||||
PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
|
||||
PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
|
||||
PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
|
||||
PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
|
||||
PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
|
||||
PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
|
||||
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
|
||||
APLL_CON0, NULL),
|
||||
|
|
@ -1538,6 +1578,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
|
|||
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
|
||||
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
|
||||
exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
|
||||
}
|
||||
|
||||
if (soc == EXYNOS5420)
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <dt-bindings/clock/exynos5433.h>
|
||||
|
||||
|
|
@ -5584,6 +5585,8 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
|
|||
|
||||
data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
|
||||
info->nr_clk_regs);
|
||||
if (!data->clk_save)
|
||||
return -ENOMEM;
|
||||
data->nr_clk_save = info->nr_clk_regs;
|
||||
data->clk_suspend = info->suspend_regs;
|
||||
data->nr_clk_suspend = info->nr_suspend_regs;
|
||||
|
|
@ -5592,12 +5595,19 @@ static int __init exynos5433_cmu_probe(struct platform_device *pdev)
|
|||
if (data->nr_pclks > 0) {
|
||||
data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
|
||||
data->nr_pclks, GFP_KERNEL);
|
||||
|
||||
if (!data->pclks) {
|
||||
kfree(data->clk_save);
|
||||
return -ENOMEM;
|
||||
}
|
||||
for (i = 0; i < data->nr_pclks; i++) {
|
||||
struct clk *clk = of_clk_get(dev->of_node, i);
|
||||
|
||||
if (IS_ERR(clk))
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(data->clk_save);
|
||||
while (--i >= 0)
|
||||
clk_put(data->pclks[i]);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
data->pclks[i] = clk;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -80,5 +80,15 @@
|
|||
#define AUD_CLKID_TDM_SCLK_PAD0 160
|
||||
#define AUD_CLKID_TDM_SCLK_PAD1 161
|
||||
#define AUD_CLKID_TDM_SCLK_PAD2 162
|
||||
#define AUD_CLKID_TOP 163
|
||||
#define AUD_CLKID_TORAM 164
|
||||
#define AUD_CLKID_EQDRC 165
|
||||
#define AUD_CLKID_RESAMPLE_B 166
|
||||
#define AUD_CLKID_TOVAD 167
|
||||
#define AUD_CLKID_LOCKER 168
|
||||
#define AUD_CLKID_SPDIFIN_LB 169
|
||||
#define AUD_CLKID_FRDDR_D 170
|
||||
#define AUD_CLKID_TODDR_D 171
|
||||
#define AUD_CLKID_LOOPBACK_B 172
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
#define IMX7ULP_CLK_NIC1_DIV 36
|
||||
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
|
||||
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
|
||||
/* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */
|
||||
#define IMX7ULP_CLK_MIPI_PLL 39
|
||||
#define IMX7ULP_CLK_SIRC 40
|
||||
#define IMX7ULP_CLK_SOSC_BUS_CLK 41
|
||||
|
|
|
|||
|
|
@ -248,6 +248,23 @@
|
|||
#define IMX8MM_CLK_SNVS_ROOT 228
|
||||
#define IMX8MM_CLK_GIC 229
|
||||
|
||||
#define IMX8MM_CLK_END 230
|
||||
#define IMX8MM_SYS_PLL1_40M_CG 230
|
||||
#define IMX8MM_SYS_PLL1_80M_CG 231
|
||||
#define IMX8MM_SYS_PLL1_100M_CG 232
|
||||
#define IMX8MM_SYS_PLL1_133M_CG 233
|
||||
#define IMX8MM_SYS_PLL1_160M_CG 234
|
||||
#define IMX8MM_SYS_PLL1_200M_CG 235
|
||||
#define IMX8MM_SYS_PLL1_266M_CG 236
|
||||
#define IMX8MM_SYS_PLL1_400M_CG 237
|
||||
#define IMX8MM_SYS_PLL2_50M_CG 238
|
||||
#define IMX8MM_SYS_PLL2_100M_CG 239
|
||||
#define IMX8MM_SYS_PLL2_125M_CG 240
|
||||
#define IMX8MM_SYS_PLL2_166M_CG 241
|
||||
#define IMX8MM_SYS_PLL2_200M_CG 242
|
||||
#define IMX8MM_SYS_PLL2_250M_CG 243
|
||||
#define IMX8MM_SYS_PLL2_333M_CG 244
|
||||
#define IMX8MM_SYS_PLL2_500M_CG 245
|
||||
|
||||
#define IMX8MM_CLK_END 246
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -211,6 +211,23 @@
|
|||
#define IMX8MN_CLK_GPU_CORE_ROOT 193
|
||||
#define IMX8MN_CLK_GIC 194
|
||||
|
||||
#define IMX8MN_CLK_END 195
|
||||
#define IMX8MN_SYS_PLL1_40M_CG 195
|
||||
#define IMX8MN_SYS_PLL1_80M_CG 196
|
||||
#define IMX8MN_SYS_PLL1_100M_CG 197
|
||||
#define IMX8MN_SYS_PLL1_133M_CG 198
|
||||
#define IMX8MN_SYS_PLL1_160M_CG 199
|
||||
#define IMX8MN_SYS_PLL1_200M_CG 200
|
||||
#define IMX8MN_SYS_PLL1_266M_CG 201
|
||||
#define IMX8MN_SYS_PLL1_400M_CG 202
|
||||
#define IMX8MN_SYS_PLL2_50M_CG 203
|
||||
#define IMX8MN_SYS_PLL2_100M_CG 204
|
||||
#define IMX8MN_SYS_PLL2_125M_CG 205
|
||||
#define IMX8MN_SYS_PLL2_166M_CG 206
|
||||
#define IMX8MN_SYS_PLL2_200M_CG 207
|
||||
#define IMX8MN_SYS_PLL2_250M_CG 208
|
||||
#define IMX8MN_SYS_PLL2_333M_CG 209
|
||||
#define IMX8MN_SYS_PLL2_500M_CG 210
|
||||
|
||||
#define IMX8MN_CLK_END 211
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -403,5 +403,27 @@
|
|||
#define IMX8MQ_CLK_SNVS_ROOT 264
|
||||
#define IMX8MQ_CLK_GIC 265
|
||||
|
||||
#define IMX8MQ_CLK_END 266
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
|
||||
|
||||
#define IMX8MQ_SYS1_PLL_40M_CG 267
|
||||
#define IMX8MQ_SYS1_PLL_80M_CG 268
|
||||
#define IMX8MQ_SYS1_PLL_100M_CG 269
|
||||
#define IMX8MQ_SYS1_PLL_133M_CG 270
|
||||
#define IMX8MQ_SYS1_PLL_160M_CG 271
|
||||
#define IMX8MQ_SYS1_PLL_200M_CG 272
|
||||
#define IMX8MQ_SYS1_PLL_266M_CG 273
|
||||
#define IMX8MQ_SYS1_PLL_400M_CG 274
|
||||
#define IMX8MQ_SYS1_PLL_800M_CG 275
|
||||
#define IMX8MQ_SYS2_PLL_50M_CG 276
|
||||
#define IMX8MQ_SYS2_PLL_100M_CG 277
|
||||
#define IMX8MQ_SYS2_PLL_125M_CG 278
|
||||
#define IMX8MQ_SYS2_PLL_166M_CG 279
|
||||
#define IMX8MQ_SYS2_PLL_200M_CG 280
|
||||
#define IMX8MQ_SYS2_PLL_250M_CG 281
|
||||
#define IMX8MQ_SYS2_PLL_333M_CG 282
|
||||
#define IMX8MQ_SYS2_PLL_500M_CG 283
|
||||
#define IMX8MQ_SYS2_PLL_1000M_CG 284
|
||||
|
||||
#define IMX8MQ_CLK_END 285
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a774b1 CPG Core Clocks */
|
||||
#define R8A774B1_CLK_Z 0
|
||||
#define R8A774B1_CLK_ZG 1
|
||||
#define R8A774B1_CLK_ZTR 2
|
||||
#define R8A774B1_CLK_ZTRD2 3
|
||||
#define R8A774B1_CLK_ZT 4
|
||||
#define R8A774B1_CLK_ZX 5
|
||||
#define R8A774B1_CLK_S0D1 6
|
||||
#define R8A774B1_CLK_S0D2 7
|
||||
#define R8A774B1_CLK_S0D3 8
|
||||
#define R8A774B1_CLK_S0D4 9
|
||||
#define R8A774B1_CLK_S0D6 10
|
||||
#define R8A774B1_CLK_S0D8 11
|
||||
#define R8A774B1_CLK_S0D12 12
|
||||
#define R8A774B1_CLK_S1D2 13
|
||||
#define R8A774B1_CLK_S1D4 14
|
||||
#define R8A774B1_CLK_S2D1 15
|
||||
#define R8A774B1_CLK_S2D2 16
|
||||
#define R8A774B1_CLK_S2D4 17
|
||||
#define R8A774B1_CLK_S3D1 18
|
||||
#define R8A774B1_CLK_S3D2 19
|
||||
#define R8A774B1_CLK_S3D4 20
|
||||
#define R8A774B1_CLK_LB 21
|
||||
#define R8A774B1_CLK_CL 22
|
||||
#define R8A774B1_CLK_ZB3 23
|
||||
#define R8A774B1_CLK_ZB3D2 24
|
||||
#define R8A774B1_CLK_CR 25
|
||||
#define R8A774B1_CLK_DDR 26
|
||||
#define R8A774B1_CLK_SD0H 27
|
||||
#define R8A774B1_CLK_SD0 28
|
||||
#define R8A774B1_CLK_SD1H 29
|
||||
#define R8A774B1_CLK_SD1 30
|
||||
#define R8A774B1_CLK_SD2H 31
|
||||
#define R8A774B1_CLK_SD2 32
|
||||
#define R8A774B1_CLK_SD3H 33
|
||||
#define R8A774B1_CLK_SD3 34
|
||||
#define R8A774B1_CLK_RPC 35
|
||||
#define R8A774B1_CLK_RPCD2 36
|
||||
#define R8A774B1_CLK_MSO 37
|
||||
#define R8A774B1_CLK_HDMI 38
|
||||
#define R8A774B1_CLK_CSI0 39
|
||||
#define R8A774B1_CLK_CP 40
|
||||
#define R8A774B1_CLK_CPEX 41
|
||||
#define R8A774B1_CLK_R 42
|
||||
#define R8A774B1_CLK_OSC 43
|
||||
#define R8A774B1_CLK_CANFD 44
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
#define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__
|
||||
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
|
||||
/* r8a77961 CPG Core Clocks */
|
||||
#define R8A77961_CLK_Z 0
|
||||
#define R8A77961_CLK_Z2 1
|
||||
#define R8A77961_CLK_ZR 2
|
||||
#define R8A77961_CLK_ZG 3
|
||||
#define R8A77961_CLK_ZTR 4
|
||||
#define R8A77961_CLK_ZTRD2 5
|
||||
#define R8A77961_CLK_ZT 6
|
||||
#define R8A77961_CLK_ZX 7
|
||||
#define R8A77961_CLK_S0D1 8
|
||||
#define R8A77961_CLK_S0D2 9
|
||||
#define R8A77961_CLK_S0D3 10
|
||||
#define R8A77961_CLK_S0D4 11
|
||||
#define R8A77961_CLK_S0D6 12
|
||||
#define R8A77961_CLK_S0D8 13
|
||||
#define R8A77961_CLK_S0D12 14
|
||||
#define R8A77961_CLK_S1D1 15
|
||||
#define R8A77961_CLK_S1D2 16
|
||||
#define R8A77961_CLK_S1D4 17
|
||||
#define R8A77961_CLK_S2D1 18
|
||||
#define R8A77961_CLK_S2D2 19
|
||||
#define R8A77961_CLK_S2D4 20
|
||||
#define R8A77961_CLK_S3D1 21
|
||||
#define R8A77961_CLK_S3D2 22
|
||||
#define R8A77961_CLK_S3D4 23
|
||||
#define R8A77961_CLK_LB 24
|
||||
#define R8A77961_CLK_CL 25
|
||||
#define R8A77961_CLK_ZB3 26
|
||||
#define R8A77961_CLK_ZB3D2 27
|
||||
#define R8A77961_CLK_ZB3D4 28
|
||||
#define R8A77961_CLK_CR 29
|
||||
#define R8A77961_CLK_CRD2 30
|
||||
#define R8A77961_CLK_SD0H 31
|
||||
#define R8A77961_CLK_SD0 32
|
||||
#define R8A77961_CLK_SD1H 33
|
||||
#define R8A77961_CLK_SD1 34
|
||||
#define R8A77961_CLK_SD2H 35
|
||||
#define R8A77961_CLK_SD2 36
|
||||
#define R8A77961_CLK_SD3H 37
|
||||
#define R8A77961_CLK_SD3 38
|
||||
#define R8A77961_CLK_SSP2 39
|
||||
#define R8A77961_CLK_SSP1 40
|
||||
#define R8A77961_CLK_SSPRS 41
|
||||
#define R8A77961_CLK_RPC 42
|
||||
#define R8A77961_CLK_RPCD2 43
|
||||
#define R8A77961_CLK_MSO 44
|
||||
#define R8A77961_CLK_CANFD 45
|
||||
#define R8A77961_CLK_HDMI 46
|
||||
#define R8A77961_CLK_CSI0 47
|
||||
/* CLK_CSIREF was removed */
|
||||
#define R8A77961_CLK_CP 49
|
||||
#define R8A77961_CLK_CPEX 50
|
||||
#define R8A77961_CLK_R 51
|
||||
#define R8A77961_CLK_OSC 52
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* Copyright (C) 2019 Renesas Electronics Corp.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A774B1_PD_CA57_CPU0 0
|
||||
#define R8A774B1_PD_CA57_CPU1 1
|
||||
#define R8A774B1_PD_A3VP 9
|
||||
#define R8A774B1_PD_CA57_SCU 12
|
||||
#define R8A774B1_PD_A3VC 14
|
||||
#define R8A774B1_PD_3DG_A 17
|
||||
#define R8A774B1_PD_3DG_B 18
|
||||
#define R8A774B1_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A774B1_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright (C) 2019 Glider bvba
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
|
||||
|
||||
/*
|
||||
* These power domain indices match the numbers of the interrupt bits
|
||||
* representing the power areas in the various Interrupt Registers
|
||||
* (e.g. SYSCISR, Interrupt Status Register)
|
||||
*/
|
||||
|
||||
#define R8A77961_PD_CA57_CPU0 0
|
||||
#define R8A77961_PD_CA57_CPU1 1
|
||||
#define R8A77961_PD_CA53_CPU0 5
|
||||
#define R8A77961_PD_CA53_CPU1 6
|
||||
#define R8A77961_PD_CA53_CPU2 7
|
||||
#define R8A77961_PD_CA53_CPU3 8
|
||||
#define R8A77961_PD_CA57_SCU 12
|
||||
#define R8A77961_PD_CR7 13
|
||||
#define R8A77961_PD_A3VC 14
|
||||
#define R8A77961_PD_3DG_A 17
|
||||
#define R8A77961_PD_3DG_B 18
|
||||
#define R8A77961_PD_CA53_SCU 21
|
||||
#define R8A77961_PD_A3IR 24
|
||||
#define R8A77961_PD_A2VC1 26
|
||||
|
||||
/* Always-on power area */
|
||||
#define R8A77961_PD_ALWAYS_ON 32
|
||||
|
||||
#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
|
||||
|
|
@ -35,4 +35,19 @@
|
|||
#define AUD_RESET_TOHDMITX 24
|
||||
#define AUD_RESET_CLKTREE 25
|
||||
|
||||
/* SM1 added resets */
|
||||
#define AUD_RESET_RESAMPLE_B 26
|
||||
#define AUD_RESET_TOVAD 27
|
||||
#define AUD_RESET_LOCKER 28
|
||||
#define AUD_RESET_SPDIFIN_LB 29
|
||||
#define AUD_RESET_FRATV 30
|
||||
#define AUD_RESET_FRHDMIRX 31
|
||||
#define AUD_RESET_FRDDR_D 32
|
||||
#define AUD_RESET_TODDR_D 33
|
||||
#define AUD_RESET_LOOPBACK_B 34
|
||||
#define AUD_RESET_EARCTX 35
|
||||
#define AUD_RESET_EARCRX 36
|
||||
#define AUD_RESET_FRDDR_E 37
|
||||
#define AUD_RESET_TODDR_E 38
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue