x86/cpu: Create Zhaoxin processors architecture support file
Add x86 architecture support for new Zhaoxin processors. Carve out initialization code needed by Zhaoxin processors into a separate compilation unit. To identify Zhaoxin CPU, add a new vendor type X86_VENDOR_ZHAOXIN for system recognition. Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: "hpa@zytor.com" <hpa@zytor.com> Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org> Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net> Cc: "lenb@kernel.org" <lenb@kernel.org> Cc: David Wang <DavidWang@zhaoxin.com> Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com> Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com> Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com> Link: https://lkml.kernel.org/r/01042674b2f741b2aed1f797359bdffb@zhaoxin.com
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@ -17477,6 +17477,12 @@ Q: https://patchwork.linuxtv.org/project/linux-media/list/
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S: Maintained
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F: drivers/media/dvb-frontends/zd1301_demod*
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ZHAOXIN PROCESSOR SUPPORT
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M: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
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L: linux-kernel@vger.kernel.org
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S: Maintained
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F: arch/x86/kernel/cpu/zhaoxin.c
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ZPOOL COMPRESSED PAGE STORAGE API
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M: Dan Streetman <ddstreet@ieee.org>
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L: linux-mm@kvack.org
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@ -480,3 +480,16 @@ config CPU_SUP_UMC_32
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CPU might render the kernel unbootable.
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If unsure, say N.
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config CPU_SUP_ZHAOXIN
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default y
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bool "Support Zhaoxin processors" if PROCESSOR_SELECT
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help
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This enables detection, tunings and quirks for Zhaoxin processors
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You need this enabled if you want your kernel to run on a
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Zhaoxin CPU. Disabling this option on other types of CPUs
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makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin
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CPU might render the kernel unbootable.
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If unsure, say N.
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@ -144,7 +144,8 @@ enum cpuid_regs_idx {
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_HYGON 9
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#define X86_VENDOR_NUM 10
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#define X86_VENDOR_ZHAOXIN 10
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#define X86_VENDOR_NUM 11
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#define X86_VENDOR_UNKNOWN 0xff
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@ -38,6 +38,7 @@ obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
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obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
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obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
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obj-$(CONFIG_CPU_SUP_UMC_32) += umc.o
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obj-$(CONFIG_CPU_SUP_ZHAOXIN) += zhaoxin.o
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obj-$(CONFIG_X86_MCE) += mce/
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obj-$(CONFIG_MTRR) += mtrr/
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167
arch/x86/kernel/cpu/zhaoxin.c
Normal file
167
arch/x86/kernel/cpu/zhaoxin.c
Normal file
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@ -0,0 +1,167 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/sched.h>
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#include <linux/sched/clock.h>
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#include <asm/cpufeature.h>
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#include "cpu.h"
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#define MSR_ZHAOXIN_FCR57 0x00001257
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#define ACE_PRESENT (1 << 6)
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#define ACE_ENABLED (1 << 7)
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#define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */
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#define RNG_PRESENT (1 << 2)
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#define RNG_ENABLED (1 << 3)
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#define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */
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#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
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#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
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#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
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#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
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#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
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#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
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static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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/* Test for Extended Feature Flags presence */
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if (cpuid_eax(0xC0000000) >= 0xC0000001) {
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u32 tmp = cpuid_edx(0xC0000001);
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/* Enable ACE unit, if present and disabled */
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if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
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rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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/* Enable ACE unit */
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lo |= ACE_FCR;
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wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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pr_info("CPU: Enabled ACE h/w crypto\n");
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}
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/* Enable RNG unit, if present and disabled */
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if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
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rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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/* Enable RNG unit */
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lo |= RNG_ENABLE;
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wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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pr_info("CPU: Enabled h/w RNG\n");
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}
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/*
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* Store Extended Feature Flags as word 5 of the CPU
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* capability bit array
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*/
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c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
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}
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if (c->x86 >= 0x6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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cpu_detect_cache_sizes(c);
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}
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static void early_init_zhaoxin(struct cpuinfo_x86 *c)
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{
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if (c->x86 >= 0x6)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#endif
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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}
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if (c->cpuid_level >= 0x00000001) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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/*
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* If HTT (EDX[28]) is set EBX[16:23] contain the number of
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* apicids which are reserved per package. Store the resulting
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* shift value for the package management code.
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*/
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if (edx & (1U << 28))
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c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
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}
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}
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static void zhaoxin_detect_vmx_virtcap(struct cpuinfo_x86 *c)
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{
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u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
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rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
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msr_ctl = vmx_msr_high | vmx_msr_low;
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
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set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
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set_cpu_cap(c, X86_FEATURE_VNMI);
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
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rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
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vmx_msr_low, vmx_msr_high);
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msr_ctl2 = vmx_msr_high | vmx_msr_low;
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if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
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(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
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set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
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if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
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set_cpu_cap(c, X86_FEATURE_EPT);
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if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
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set_cpu_cap(c, X86_FEATURE_VPID);
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}
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}
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static void init_zhaoxin(struct cpuinfo_x86 *c)
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{
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early_init_zhaoxin(c);
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init_intel_cacheinfo(c);
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detect_num_cpu_cores(c);
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#ifdef CONFIG_X86_32
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detect_ht(c);
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#endif
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if (c->cpuid_level > 9) {
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unsigned int eax = cpuid_eax(10);
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/*
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* Check for version and the number of counters
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* Version(eax[7:0]) can't be 0;
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* Counters(eax[15:8]) should be greater than 1;
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*/
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if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (c->x86 >= 0x6)
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init_zhaoxin_cap(c);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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#endif
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if (cpu_has(c, X86_FEATURE_VMX))
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zhaoxin_detect_vmx_virtcap(c);
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}
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#ifdef CONFIG_X86_32
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static unsigned int
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zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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return size;
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}
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#endif
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static const struct cpu_dev zhaoxin_cpu_dev = {
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.c_vendor = "zhaoxin",
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.c_ident = { " Shanghai " },
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.c_early_init = early_init_zhaoxin,
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.c_init = init_zhaoxin,
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#ifdef CONFIG_X86_32
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.legacy_cache_size = zhaoxin_size_cache,
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#endif
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.c_x86_vendor = X86_VENDOR_ZHAOXIN,
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};
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cpu_dev_register(zhaoxin_cpu_dev);
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