ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
Get rid of core pll frequency set in platform code as we set it via device tree using 'assigned-clock-rates' property. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -38,42 +38,6 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
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#define CREG_CORE_IF_CLK_DIV_2 0x1
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#define CGU_BASE ARC_PERIPHERAL_BASE
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#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
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#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
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#define CGU_PLL_STATUS_LOCK BIT(0)
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#define CGU_PLL_STATUS_ERR BIT(1)
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#define CGU_PLL_CTRL_1GHZ 0x3A10
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#define HSDK_PLL_LOCK_TIMEOUT 500
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#define HSDK_PLL_LOCKED() \
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!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
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#define HSDK_PLL_ERR() \
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!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
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static void __init hsdk_set_cpu_freq_1ghz(void)
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{
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u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
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/*
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* As we set cpu clock which exceeds 500MHz, the divider for the interface
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* clock must be programmed to div-by-2.
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*/
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iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
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/* Set cpu clock to 1GHz */
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iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
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while (!HSDK_PLL_LOCKED() && timeout--)
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cpu_relax();
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if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
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pr_err("Failed to setup CPU frequency to 1GHz!");
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}
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
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#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
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@ -98,12 +62,6 @@ static void __init hsdk_init_early(void)
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* minimum possible div-by-2.
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*/
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iowrite32(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT);
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/*
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* Setup CPU frequency to 1GHz.
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* TODO: remove it after smart hsdk pll driver will be introduced.
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*/
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hsdk_set_cpu_freq_1ghz();
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}
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static const char *hsdk_compat[] __initconst = {
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