irqchip/gic-v3: Dynamically allocate PPI NMI refcounts
As we're about to have a variable number of PPIs, let's make the allocation of the NMI refcounts dynamic. Also apply some minor cleanups (moving things around). Signed-off-by: Marc Zyngier <maz@kernel.org>
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@ -88,7 +88,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
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static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
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/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
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/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
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static refcount_t ppi_nmi_refs[16];
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static refcount_t *ppi_nmi_refs;
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static struct gic_kvm_info gic_v3_kvm_info;
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static struct gic_kvm_info gic_v3_kvm_info;
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static DEFINE_PER_CPU(bool, has_rss);
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static DEFINE_PER_CPU(bool, has_rss);
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@ -409,6 +409,16 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
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writeb_relaxed(prio, base + offset + index);
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writeb_relaxed(prio, base + offset + index);
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}
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}
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static u32 gic_get_ppi_index(struct irq_data *d)
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{
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switch (get_intid_range(d)) {
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case PPI_RANGE:
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return d->hwirq - 16;
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default:
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unreachable();
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}
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}
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static int gic_irq_nmi_setup(struct irq_data *d)
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static int gic_irq_nmi_setup(struct irq_data *d)
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{
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{
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struct irq_desc *desc = irq_to_desc(d->irq);
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struct irq_desc *desc = irq_to_desc(d->irq);
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@ -429,10 +439,12 @@ static int gic_irq_nmi_setup(struct irq_data *d)
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return -EINVAL;
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return -EINVAL;
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/* desc lock should already be held */
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/* desc lock should already be held */
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if (gic_irq(d) < 32) {
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if (gic_irq_in_rdist(d)) {
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u32 idx = gic_get_ppi_index(d);
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/* Setting up PPI as NMI, only switch handler for first NMI */
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/* Setting up PPI as NMI, only switch handler for first NMI */
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if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) {
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if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
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refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1);
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refcount_set(&ppi_nmi_refs[idx], 1);
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desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
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desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
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}
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}
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} else {
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} else {
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@ -464,9 +476,11 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
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return;
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return;
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/* desc lock should already be held */
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/* desc lock should already be held */
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if (gic_irq(d) < 32) {
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if (gic_irq_in_rdist(d)) {
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u32 idx = gic_get_ppi_index(d);
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/* Tearing down NMI, only switch handler for last NMI */
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/* Tearing down NMI, only switch handler for last NMI */
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if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16]))
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if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
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desc->handle_irq = handle_percpu_devid_irq;
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desc->handle_irq = handle_percpu_devid_irq;
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} else {
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} else {
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desc->handle_irq = handle_fasteoi_irq;
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desc->handle_irq = handle_fasteoi_irq;
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@ -1394,7 +1408,19 @@ static void gic_enable_nmi_support(void)
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{
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{
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int i;
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int i;
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for (i = 0; i < 16; i++)
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if (!gic_prio_masking_enabled())
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return;
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if (gic_has_group0() && !gic_dist_security_disabled()) {
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pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
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return;
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}
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ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
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if (!ppi_nmi_refs)
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return;
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for (i = 0; i < gic_data.ppi_nr; i++)
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refcount_set(&ppi_nmi_refs[i], 0);
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refcount_set(&ppi_nmi_refs[i], 0);
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static_branch_enable(&supports_pseudo_nmis);
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static_branch_enable(&supports_pseudo_nmis);
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@ -1472,12 +1498,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
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gicv2m_init(handle, gic_data.domain);
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gicv2m_init(handle, gic_data.domain);
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}
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}
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if (gic_prio_masking_enabled()) {
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if (!gic_has_group0() || gic_dist_security_disabled())
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gic_enable_nmi_support();
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gic_enable_nmi_support();
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else
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pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
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}
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return 0;
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return 0;
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