clk: imx: Fix reparenting of UARTs not associated with stdout
[ Upstream commitpull/339/head^2379c9a24cc] Most if not all i.MX SoC's call a function which enables all UARTS. This is a problem for users who need to re-parent the clock source, because any attempt to change the parent results in an busy error due to the fact that the clocks have been enabled already. clk: failed to reparent uart1 to sys_pll1_80m: -16 Instead of pre-initializing all UARTS, scan the device tree to see which UART clocks are associated to stdout, and only enable those UART clocks if it's needed early. This will move initialization of the remaining clocks until after the parenting of the clocks. When the clocks are shutdown, this mechanism will also disable any clocks that were pre-initialized. Fixes:9461f7b33d("clk: fix CLK_SET_RATE_GATE with clock rate protection") Suggested-by: Aisheng Dong <aisheng.dong@nxp.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
Adam Ford
Greg Kroah-Hartman
parent
60ade0d56b
commit
9e33e261b4
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@ -73,16 +73,6 @@ enum mx25_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[uart_ipg_per],
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&clk[uart1_ipg],
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&clk[uart2_ipg],
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&clk[uart3_ipg],
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&clk[uart4_ipg],
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&clk[uart5_ipg],
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NULL
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};
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static int __init __mx25_clocks_init(void __iomem *ccm_base)
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{
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BUG_ON(!ccm_base);
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@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
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*/
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clk_set_parent(clk[cko_sel], clk[ipg]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(6);
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return 0;
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}
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@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX27_CLK_PER1_GATE],
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&clk[IMX27_CLK_UART1_IPG_GATE],
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&clk[IMX27_CLK_UART2_IPG_GATE],
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&clk[IMX27_CLK_UART3_IPG_GATE],
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&clk[IMX27_CLK_UART4_IPG_GATE],
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&clk[IMX27_CLK_UART5_IPG_GATE],
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&clk[IMX27_CLK_UART6_IPG_GATE],
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NULL
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};
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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BUG_ON(!ccm);
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@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(7);
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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@ -82,14 +82,6 @@ enum mx35_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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NULL
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};
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static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void)
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(4);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
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static struct clk *clk[IMX5_CLK_END];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks_mx51[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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NULL
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};
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static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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&clk[IMX5_CLK_UART4_IPG_GATE],
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&clk[IMX5_CLK_UART4_PER_GATE],
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&clk[IMX5_CLK_UART5_IPG_GATE],
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&clk[IMX5_CLK_UART5_PER_GATE],
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NULL
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};
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static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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{
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clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np)
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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imx_register_uart_clocks(uart_clks_mx51);
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imx_register_uart_clocks(3);
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}
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CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
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@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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@ -140,13 +140,6 @@ static inline int clk_on_imx6dl(void)
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return of_machine_is_compatible("fsl,imx6dl");
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6QDL_CLK_UART_IPG,
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IMX6QDL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static int ldb_di_sel_by_clock_id(int clock_id)
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{
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switch (clock_id) {
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@ -440,7 +433,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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struct device_node *np;
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void __iomem *anatop_base, *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6QDL_CLK_END), GFP_KERNEL);
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@ -982,12 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
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}
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(1);
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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@ -178,19 +178,11 @@ void imx6sl_set_wait_clk(bool enter)
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imx6sl_enable_pll_arm(false);
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6SL_CLK_UART,
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IMX6SL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SL_CLK_END), GFP_KERNEL);
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@ -447,12 +439,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
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hws[IMX6SL_CLK_PLL2_PFD2]->clk);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
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@ -76,26 +76,10 @@ static u32 share_count_ssi1;
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static u32 share_count_ssi2;
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static u32 share_count_ssi3;
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static const int uart_clk_ids[] __initconst = {
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IMX6SLL_CLK_UART1_IPG,
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IMX6SLL_CLK_UART1_SERIAL,
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IMX6SLL_CLK_UART2_IPG,
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IMX6SLL_CLK_UART2_SERIAL,
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IMX6SLL_CLK_UART3_IPG,
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IMX6SLL_CLK_UART3_SERIAL,
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IMX6SLL_CLK_UART4_IPG,
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IMX6SLL_CLK_UART4_SERIAL,
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IMX6SLL_CLK_UART5_IPG,
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IMX6SLL_CLK_UART5_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SLL_CLK_END), GFP_KERNEL);
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@ -356,13 +340,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(5);
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/* Lower the AHB clock rate before changing the clock source. */
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clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
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@ -117,18 +117,10 @@ static u32 share_count_ssi3;
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static u32 share_count_sai1;
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static u32 share_count_sai2;
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static const int uart_clk_ids[] __initconst = {
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IMX6SX_CLK_UART_IPG,
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IMX6SX_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SX_CLK_CLK_END), GFP_KERNEL);
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@ -556,12 +548,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
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@ -377,23 +377,10 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
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static struct clk_hw **hws;
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static struct clk_hw_onecell_data *clk_hw_data;
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static const int uart_clk_ids[] __initconst = {
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IMX7D_UART1_ROOT_CLK,
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IMX7D_UART2_ROOT_CLK,
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IMX7D_UART3_ROOT_CLK,
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IMX7D_UART4_ROOT_CLK,
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IMX7D_UART5_ROOT_CLK,
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IMX7D_UART6_ROOT_CLK,
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IMX7D_UART7_ROOT_CLK,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx7d_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX7D_CLK_END), GFP_KERNEL);
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@ -897,14 +884,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
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hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(7);
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}
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CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
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@ -43,19 +43,6 @@ static const struct clk_div_table ulp_div_table[] = {
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{ /* sentinel */ },
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};
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static const int pcc2_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART4,
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IMX7ULP_CLK_LPUART5,
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};
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static const int pcc3_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART6,
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IMX7ULP_CLK_LPUART7,
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};
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static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
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static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
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static void __init imx7ulp_clk_scg1_init(struct device_node *np)
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{
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struct clk_hw_onecell_data *clk_data;
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@ -150,7 +137,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw **hws;
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void __iomem *base;
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int i;
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clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
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GFP_KERNEL);
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@ -190,13 +176,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
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for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
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int index = pcc2_uart_clk_ids[i];
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pcc2_uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(pcc2_uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
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@ -205,7 +185,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
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struct clk_hw_onecell_data *clk_data;
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struct clk_hw **hws;
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void __iomem *base;
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int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
|
||||
GFP_KERNEL);
|
||||
|
|
@ -244,13 +223,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
|||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
|
||||
int index = pcc3_uart_clk_ids[i];
|
||||
|
||||
pcc3_uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc3_uart_clks);
|
||||
imx_register_uart_clocks(7);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -291,20 +291,12 @@ static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MM_CLK_UART1_ROOT,
|
||||
IMX8MM_CLK_UART2_ROOT,
|
||||
IMX8MM_CLK_UART3_ROOT,
|
||||
IMX8MM_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MM_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -622,13 +614,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -284,20 +284,12 @@ static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sy
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MN_CLK_UART1_ROOT,
|
||||
IMX8MN_CLK_UART2_ROOT,
|
||||
IMX8MN_CLK_UART3_ROOT,
|
||||
IMX8MN_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MN_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -573,13 +565,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -414,20 +414,11 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r
|
|||
static struct clk_hw **hws;
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MP_CLK_UART1_ROOT,
|
||||
IMX8MP_CLK_UART2_ROOT,
|
||||
IMX8MP_CLK_UART3_ROOT,
|
||||
IMX8MP_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *anatop_base, *ccm_base;
|
||||
int i;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
|
|
@ -737,13 +728,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -273,20 +273,12 @@ static const char * const imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sy
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MQ_CLK_UART1_ROOT,
|
||||
IMX8MQ_CLK_UART2_ROOT,
|
||||
IMX8MQ_CLK_UART3_ROOT,
|
||||
IMX8MQ_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int err, i;
|
||||
int err;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MQ_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -607,13 +599,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -147,8 +147,10 @@ void imx_cscmr1_fixup(u32 *val)
|
|||
}
|
||||
|
||||
#ifndef MODULE
|
||||
static int imx_keep_uart_clocks;
|
||||
static struct clk ** const *imx_uart_clocks;
|
||||
|
||||
static bool imx_keep_uart_clocks;
|
||||
static int imx_enabled_uart_clocks;
|
||||
static struct clk **imx_uart_clocks;
|
||||
|
||||
static int __init imx_keep_uart_clocks_param(char *str)
|
||||
{
|
||||
|
|
@ -161,24 +163,45 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
|
|||
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
|
||||
void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
imx_enabled_uart_clocks = 0;
|
||||
|
||||
/* i.MX boards use device trees now. For build tests without CONFIG_OF, do nothing */
|
||||
#ifdef CONFIG_OF
|
||||
if (imx_keep_uart_clocks) {
|
||||
int i;
|
||||
|
||||
imx_uart_clocks = clks;
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_prepare_enable(*imx_uart_clocks[i]);
|
||||
imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
|
||||
|
||||
if (!of_stdout)
|
||||
return;
|
||||
|
||||
for (i = 0; i < clk_count; i++) {
|
||||
imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
|
||||
|
||||
/* Stop if there are no more of_stdout references */
|
||||
if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
|
||||
return;
|
||||
|
||||
/* Only enable the clock if it's not NULL */
|
||||
if (imx_uart_clocks[imx_enabled_uart_clocks])
|
||||
clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static int __init imx_clk_disable_uart(void)
|
||||
{
|
||||
if (imx_keep_uart_clocks && imx_uart_clocks) {
|
||||
if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
|
||||
int i;
|
||||
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_disable_unprepare(*imx_uart_clocks[i]);
|
||||
for (i = 0; i < imx_enabled_uart_clocks; i++) {
|
||||
clk_disable_unprepare(imx_uart_clocks[i]);
|
||||
clk_put(imx_uart_clocks[i]);
|
||||
}
|
||||
kfree(imx_uart_clocks);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -13,9 +13,9 @@ extern spinlock_t imx_ccm_lock;
|
|||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
#ifndef MODULE
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks(unsigned int clk_count);
|
||||
#else
|
||||
static inline void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
static inline void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue