dmaengine: pl08x: support dt channel assignment
Add support for assigning DMA channels from a device tree. [je: remove channel sub-node parsing, dynamic channel creation on xlate] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Linus Walleij
Vinod Koul
parent
4a736d156d
commit
aa4734da66
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@ -83,6 +83,8 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/pm_runtime.h>
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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@ -2030,10 +2032,188 @@ static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
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}
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#endif
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#ifdef CONFIG_OF
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static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x,
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u32 id)
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{
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struct pl08x_dma_chan *chan;
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list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
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if (chan->signal == id)
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return &chan->vc.chan;
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}
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return NULL;
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}
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static struct dma_chan *pl08x_of_xlate(struct of_phandle_args *dma_spec,
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struct of_dma *ofdma)
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{
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struct pl08x_driver_data *pl08x = ofdma->of_dma_data;
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struct pl08x_channel_data *data;
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struct pl08x_dma_chan *chan;
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struct dma_chan *dma_chan;
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if (!pl08x)
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return NULL;
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if (dma_spec->args_count != 2)
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return NULL;
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dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);
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if (dma_chan)
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return dma_get_slave_channel(dma_chan);
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chan = devm_kzalloc(pl08x->slave.dev, sizeof(*chan) + sizeof(*data),
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GFP_KERNEL);
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if (!chan)
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return NULL;
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data = (void *)&chan[1];
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data->bus_id = "(none)";
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data->periph_buses = dma_spec->args[1];
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chan->cd = data;
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chan->host = pl08x;
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chan->slave = true;
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chan->name = data->bus_id;
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chan->state = PL08X_CHAN_IDLE;
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chan->signal = dma_spec->args[0];
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chan->vc.desc_free = pl08x_desc_free;
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vchan_init(&chan->vc, &pl08x->slave);
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return dma_get_slave_channel(&chan->vc.chan);
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}
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static int pl08x_of_probe(struct amba_device *adev,
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struct pl08x_driver_data *pl08x,
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struct device_node *np)
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{
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struct pl08x_platform_data *pd;
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u32 cctl_memcpy = 0;
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u32 val;
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int ret;
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pd = devm_kzalloc(&adev->dev, sizeof(*pd), GFP_KERNEL);
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if (!pd)
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return -ENOMEM;
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/* Eligible bus masters for fetching LLIs */
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if (of_property_read_bool(np, "lli-bus-interface-ahb1"))
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pd->lli_buses |= PL08X_AHB1;
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if (of_property_read_bool(np, "lli-bus-interface-ahb2"))
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pd->lli_buses |= PL08X_AHB2;
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if (!pd->lli_buses) {
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dev_info(&adev->dev, "no bus masters for LLIs stated, assume all\n");
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pd->lli_buses |= PL08X_AHB1 | PL08X_AHB2;
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}
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/* Eligible bus masters for memory access */
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if (of_property_read_bool(np, "mem-bus-interface-ahb1"))
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pd->mem_buses |= PL08X_AHB1;
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if (of_property_read_bool(np, "mem-bus-interface-ahb2"))
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pd->mem_buses |= PL08X_AHB2;
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if (!pd->mem_buses) {
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dev_info(&adev->dev, "no bus masters for memory stated, assume all\n");
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pd->mem_buses |= PL08X_AHB1 | PL08X_AHB2;
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}
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/* Parse the memcpy channel properties */
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ret = of_property_read_u32(np, "memcpy-burst-size", &val);
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if (ret) {
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dev_info(&adev->dev, "no memcpy burst size specified, using 1 byte\n");
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val = 1;
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}
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switch (val) {
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default:
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dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");
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/* Fall through */
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case 1:
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cctl_memcpy |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 4:
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cctl_memcpy |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 8:
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cctl_memcpy |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 16:
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cctl_memcpy |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 32:
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cctl_memcpy |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 64:
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cctl_memcpy |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 128:
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cctl_memcpy |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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case 256:
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cctl_memcpy |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |
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PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT;
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break;
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}
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ret = of_property_read_u32(np, "memcpy-bus-width", &val);
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if (ret) {
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dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n");
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val = 8;
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}
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switch (val) {
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default:
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dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");
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/* Fall through */
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case 8:
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cctl_memcpy |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
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PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
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break;
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case 16:
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cctl_memcpy |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT |
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PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
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break;
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case 32:
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cctl_memcpy |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
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PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
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break;
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}
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/* This is currently the only thing making sense */
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cctl_memcpy |= PL080_CONTROL_PROT_SYS;
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/* Set up memcpy channel */
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pd->memcpy_channel.bus_id = "memcpy";
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pd->memcpy_channel.cctl_memcpy = cctl_memcpy;
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/* Use the buses that can access memory, obviously */
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pd->memcpy_channel.periph_buses = pd->mem_buses;
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pl08x->pd = pd;
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return of_dma_controller_register(adev->dev.of_node, pl08x_of_xlate,
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pl08x);
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}
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#else
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static inline int pl08x_of_probe(struct amba_device *adev,
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struct pl08x_driver_data *pl08x,
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struct device_node *np)
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{
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return -EINVAL;
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}
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#endif
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static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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{
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struct pl08x_driver_data *pl08x;
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const struct vendor_data *vd = id->data;
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struct device_node *np = adev->dev.of_node;
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u32 tsfr_size;
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int ret = 0;
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int i;
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@ -2093,9 +2273,15 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
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/* Get the platform data */
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pl08x->pd = dev_get_platdata(&adev->dev);
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if (!pl08x->pd) {
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dev_err(&adev->dev, "no platform data supplied\n");
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ret = -EINVAL;
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goto out_no_platdata;
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if (np) {
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ret = pl08x_of_probe(adev, pl08x, np);
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if (ret)
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goto out_no_platdata;
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} else {
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dev_err(&adev->dev, "no platform data supplied\n");
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ret = -EINVAL;
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goto out_no_platdata;
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}
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}
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/* Assign useful pointers to the driver state */
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