phy: rcar-gen3-usb2: remove HSUSB registers handling
Since the related driver (CPG/MSSR driver) only manages the first module clock, this driver should not handle the HSUSB registers. So, this patch removes the HSUSB registers handling. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Yoshihiro Shimoda
Kishon Vijay Abraham I
parent
605df8af33
commit
b956401699
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@ -7,33 +7,26 @@ Required properties:
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- compatible: "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
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SoC.
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- reg: offset and length of the partial USB 2.0 Host register block.
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- reg-names: must be "usb2_host".
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- clocks: clock phandle and specifier pair(s).
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- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
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Optional properties:
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To use a USB channel where USB 2.0 Host and HSUSB (USB 2.0 Peripheral) are
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combined, the device tree node should set HSUSB properties to reg and reg-names
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properties. This is because HSUSB has registers to select USB 2.0 host or
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peripheral at that channel:
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- reg: offset and length of the partial HSUSB register block.
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- reg-names: must be "hsusb".
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combined, the device tree node should set interrupt properties to use the
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channel as USB OTG:
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- interrupts: interrupt specifier for the PHY.
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Example (R-Car H3):
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usb-phy@ee080200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee080200 0 0x700>, <0 0xe6590100 0 0x100>;
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reg-names = "usb2_host", "hsusb";
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reg = <0 0xee080200 0 0x700>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>,
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<&mstp7_clks R8A7795_CLK_HSUSB>;
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
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};
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usb-phy@ee0a0200 {
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compatible = "renesas,usb2-phy-r8a7795";
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reg = <0 0xee0a0200 0 0x700>;
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reg-names = "usb2_host";
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clocks = <&mstp7_clks R8A7795_CLK_EHCI0>;
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};
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@ -74,20 +74,6 @@
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#define USB2_ADPCTRL_IDPULLUP BIT(5) /* 1 = ID sampling is enabled */
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#define USB2_ADPCTRL_DRVVBUS BIT(4)
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/******* HSUSB registers (original offset is +0x100) *******/
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#define HSUSB_LPSTS 0x02
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#define HSUSB_UGCTRL2 0x84
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/* Low Power Status register (LPSTS) */
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#define HSUSB_LPSTS_SUSPM 0x4000
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/* USB General control register 2 (UGCTRL2) */
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#define HSUSB_UGCTRL2_MASK 0x00000031 /* bit[31:6] should be 0 */
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#define HSUSB_UGCTRL2_USB0SEL 0x00000030
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#define HSUSB_UGCTRL2_USB0SEL_HOST 0x00000010
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#define HSUSB_UGCTRL2_USB0SEL_HS_USB 0x00000020
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#define HSUSB_UGCTRL2_USB0SEL_OTG 0x00000030
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struct rcar_gen3_data {
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void __iomem *base;
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struct clk *clk;
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@ -95,8 +81,8 @@ struct rcar_gen3_data {
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struct rcar_gen3_chan {
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struct rcar_gen3_data usb2;
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struct rcar_gen3_data hsusb;
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struct phy *phy;
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bool has_otg;
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};
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static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
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@ -202,24 +188,15 @@ static int rcar_gen3_phy_usb2_init(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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/* Initialize USB2 part */
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writel(USB2_INT_ENABLE_INIT, usb2_base + USB2_INT_ENABLE);
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writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
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writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
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/* Initialize HSUSB part */
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if (hsusb_base) {
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val = readl(hsusb_base + HSUSB_UGCTRL2);
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val = (val & ~HSUSB_UGCTRL2_USB0SEL) |
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HSUSB_UGCTRL2_USB0SEL_OTG;
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writel(val & HSUSB_UGCTRL2_MASK, hsusb_base + HSUSB_UGCTRL2);
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/* Initialize otg part */
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/* Initialize otg part */
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if (channel->has_otg)
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rcar_gen3_init_otg(channel);
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}
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return 0;
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}
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@ -237,7 +214,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *usb2_base = channel->usb2.base;
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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val = readl(usb2_base + USB2_USBCTR);
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@ -246,33 +222,6 @@ static int rcar_gen3_phy_usb2_power_on(struct phy *p)
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val &= ~USB2_USBCTR_PLL_RST;
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writel(val, usb2_base + USB2_USBCTR);
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/*
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* TODO: To reduce power consuming, this driver should set the SUSPM
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* after the PHY detects ID pin as peripheral.
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*/
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if (hsusb_base) {
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/* Power on HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val |= HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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static int rcar_gen3_phy_usb2_power_off(struct phy *p)
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{
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struct rcar_gen3_chan *channel = phy_get_drvdata(p);
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void __iomem *hsusb_base = channel->hsusb.base;
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u32 val;
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if (hsusb_base) {
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/* Power off HSUSB PHY */
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val = readw(hsusb_base + HSUSB_LPSTS);
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val &= ~HSUSB_LPSTS_SUSPM;
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writew(val, hsusb_base + HSUSB_LPSTS);
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}
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return 0;
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}
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@ -280,7 +229,6 @@ static struct phy_ops rcar_gen3_phy_usb2_ops = {
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.init = rcar_gen3_phy_usb2_init,
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.exit = rcar_gen3_phy_usb2_exit,
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.power_on = rcar_gen3_phy_usb2_power_on,
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.power_off = rcar_gen3_phy_usb2_power_off,
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.owner = THIS_MODULE,
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};
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@ -313,6 +261,7 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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struct rcar_gen3_chan *channel;
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struct phy_provider *provider;
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struct resource *res;
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int irq;
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if (!dev->of_node) {
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dev_err(dev, "This driver needs device tree\n");
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@ -323,29 +272,19 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
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if (!channel)
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return -ENOMEM;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usb2_host");
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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channel->usb2.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->usb2.base))
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return PTR_ERR(channel->usb2.base);
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/* "hsusb" memory resource is optional */
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsusb");
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/* To avoid error message by devm_ioremap_resource() */
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if (res) {
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int irq;
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channel->hsusb.base = devm_ioremap_resource(dev, res);
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if (IS_ERR(channel->hsusb.base))
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channel->hsusb.base = NULL;
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/* call request_irq for OTG */
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irq = platform_get_irq(pdev, 0);
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if (irq >= 0)
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irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
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IRQF_SHARED, dev_name(dev),
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channel);
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/* call request_irq for OTG */
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irq = platform_get_irq(pdev, 0);
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if (irq >= 0) {
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irq = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
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IRQF_SHARED, dev_name(dev), channel);
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if (irq < 0)
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dev_err(dev, "No irq handler (%d)\n", irq);
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channel->has_otg = true;
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}
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/* devm_phy_create() will call pm_runtime_enable(dev); */
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