xtensa fixes for v5.0-rc5
- fix ccount_timer_shutdown for secondary CPUs; - fix secondary CPU initialization; - fix secondary CPU reset vector clash with double exception vector; - fix present CPUs when booting with 'maxcpus' parameter; - limit possible CPUs by configured NR_CPUS; - issue a warning if xtensa PIC is asked to retrigger anything other than software IRQ; - fix masking/unmasking of the first two IRQs on xtensa MX PIC; - fix typo in Kconfig description for user space unaligned access feature; - fix Kconfig warning for selecting BUILTIN_DTB. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEK2eFS5jlMn3N6xfYUfnMkfg/oEQFAlxUn8MTHGpjbXZia2Jj QGdtYWlsLmNvbQAKCRBR+cyR+D+gRAX6D/4oOJd7TghbVdSC82rIQXRBxmlWB1YV tPtb/W3qrkkM8c693FbAoLFNoikYFftzn4EomTz1KtkBxq7HjZmmphiTU5E23Zg5 nonnBkcFnm4Yfr4gLaTJl3rMqJNbDTMg6EyCPRHVI43Ux1jA9j/T2MN/dMZox+5a PU2q8k/HHDAlumOPj93MIKBb8XA9Sq9Jfpw2Jnlc0r8b4fR/9pKfVPOcsqs/jv3x BFIIH/vPvl2/j+DShpFcYnK8VgRo6zj2ny343J4zYqXspky43ZMMIaE/ZpkT592b uheDQYHAHvpZT+FD8waE5P5quBS5P+CmZIbuz7YTxB1VTcoV+OGGCpAvpj5CqmNr Mj2f3Yar+4q/QczHP+/42zGVDoJ/3dLBIu9IqSjWkY90qgncd9TD+dMWzI2ejJU7 LPMIAw//Y/L4m3TAg84GFfGkOjzGQUXGQGl+9sqIr3eOWgoouXatq6L4F2CxCnz2 zMKT0HFzdxs1gt13oRngugyfK1xRF0H5DW2eNt4dsFURIeIUP5cqou0v+b+CA3Li sbvI6yJ0g9tRf1f0yDnSRlvm0nB56zsXKGz5uuD6MiMOleUM3N41+IqCPHwuH0F1 wNyYSWZEkt1t88rQxnter1+sDpi4brW0BZMVUSHsf+USqcwMrwu9ZmFKj08nihMP dCEHHlVGizOEsQ== =Pim9 -----END PGP SIGNATURE----- Merge tag 'xtensa-20190201' of git://github.com/jcmvbkbc/linux-xtensa Pull xtensa fixes from Max Filippov: - fix ccount_timer_shutdown for secondary CPUs - fix secondary CPU initialization - fix secondary CPU reset vector clash with double exception vector - fix present CPUs when booting with 'maxcpus' parameter - limit possible CPUs by configured NR_CPUS - issue a warning if xtensa PIC is asked to retrigger anything other than software IRQ - fix masking/unmasking of the first two IRQs on xtensa MX PIC - fix typo in Kconfig description for user space unaligned access feature - fix Kconfig warning for selecting BUILTIN_DTB * tag 'xtensa-20190201' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: SMP: limit number of possible CPUs by NR_CPUS xtensa: rename BUILTIN_DTB to BUILTIN_DTB_SOURCE xtensa: Fix typo use space=>user space drivers/irqchip: xtensa-mx: fix mask and unmask drivers/irqchip: xtensa: add warning to irq_retrigger xtensa: SMP: mark each possible CPU as present xtensa: smp_lx200_defconfig: fix vectors clash xtensa: SMP: fix secondary CPU initialization xtensa: SMP: fix ccount_timer_shutdown
This commit is contained in:
commit
cd984a5be2
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@ -164,7 +164,7 @@ config XTENSA_FAKE_NMI
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If unsure, say N.
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config XTENSA_UNALIGNED_USER
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bool "Unaligned memory access in use space"
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bool "Unaligned memory access in user space"
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help
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The Xtensa architecture currently does not handle unaligned
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memory accesses in hardware but through an exception handler.
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@ -451,7 +451,7 @@ config USE_OF
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help
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Include support for flattened device tree machine descriptions.
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config BUILTIN_DTB
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config BUILTIN_DTB_SOURCE
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string "DTB to build into the kernel image"
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depends on OF
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@ -7,9 +7,9 @@
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#
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#
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BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o
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ifneq ($(CONFIG_BUILTIN_DTB),"")
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obj-$(CONFIG_OF) += $(BUILTIN_DTB)
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BUILTIN_DTB_SOURCE := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_SOURCE)).dtb.o
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ifneq ($(CONFIG_BUILTIN_DTB_SOURCE),"")
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obj-$(CONFIG_OF) += $(BUILTIN_DTB_SOURCE)
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endif
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# for CONFIG_OF_ALL_DTBS test
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@ -34,7 +34,7 @@ CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000@0"
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="kc705"
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CONFIG_BUILTIN_DTB_SOURCE="kc705"
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# CONFIG_COMPACTION is not set
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_PM=y
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@ -38,7 +38,7 @@ CONFIG_HIGHMEM=y
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# CONFIG_PCI is not set
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CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="csp"
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CONFIG_BUILTIN_DTB_SOURCE="csp"
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# CONFIG_COMPACTION is not set
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CONFIG_XTFPGA_LCD=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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@ -33,7 +33,7 @@ CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=0x38000000@0"
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="kc705"
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CONFIG_BUILTIN_DTB_SOURCE="kc705"
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# CONFIG_COMPACTION is not set
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_NET=y
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@ -39,7 +39,7 @@ CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=256M@0x60000000"
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="kc705_nommu"
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CONFIG_BUILTIN_DTB_SOURCE="kc705_nommu"
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CONFIG_BINFMT_FLAT=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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@ -33,11 +33,12 @@ CONFIG_SMP=y
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CONFIG_HOTPLUG_CPU=y
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# CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX is not set
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# CONFIG_PCI is not set
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CONFIG_VECTORS_OFFSET=0x00002000
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CONFIG_XTENSA_PLATFORM_XTFPGA=y
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CONFIG_CMDLINE_BOOL=y
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CONFIG_CMDLINE="earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug memmap=96M@0"
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CONFIG_USE_OF=y
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CONFIG_BUILTIN_DTB="lx200mx"
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CONFIG_BUILTIN_DTB_SOURCE="lx200mx"
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# CONFIG_COMPACTION is not set
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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CONFIG_NET=y
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@ -276,12 +276,13 @@ should_never_return:
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movi a2, cpu_start_ccount
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1:
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memw
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l32i a3, a2, 0
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beqi a3, 0, 1b
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movi a3, 0
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s32i a3, a2, 0
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memw
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1:
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memw
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l32i a3, a2, 0
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beqi a3, 0, 1b
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wsr a3, ccount
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@ -317,11 +318,13 @@ ENTRY(cpu_restart)
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rsr a0, prid
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neg a2, a0
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movi a3, cpu_start_id
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memw
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s32i a2, a3, 0
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#if XCHAL_DCACHE_IS_WRITEBACK
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dhwbi a3, 0
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#endif
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1:
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memw
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l32i a2, a3, 0
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dhi a3, 0
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bne a2, a0, 1b
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@ -83,7 +83,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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unsigned i;
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for (i = 0; i < max_cpus; ++i)
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for_each_possible_cpu(i)
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set_cpu_present(i, true);
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}
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@ -96,6 +96,11 @@ void __init smp_init_cpus(void)
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pr_info("%s: Core Count = %d\n", __func__, ncpus);
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pr_info("%s: Core Id = %d\n", __func__, core_id);
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if (ncpus > NR_CPUS) {
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ncpus = NR_CPUS;
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pr_info("%s: limiting core count by %d\n", __func__, ncpus);
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}
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for (i = 0; i < ncpus; ++i)
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set_cpu_possible(i, true);
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}
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@ -195,9 +200,11 @@ static int boot_secondary(unsigned int cpu, struct task_struct *ts)
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int i;
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#ifdef CONFIG_HOTPLUG_CPU
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cpu_start_id = cpu;
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system_flush_invalidate_dcache_range(
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(unsigned long)&cpu_start_id, sizeof(cpu_start_id));
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WRITE_ONCE(cpu_start_id, cpu);
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/* Pairs with the third memw in the cpu_restart */
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mb();
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system_flush_invalidate_dcache_range((unsigned long)&cpu_start_id,
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sizeof(cpu_start_id));
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#endif
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smp_call_function_single(0, mx_cpu_start, (void *)cpu, 1);
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@ -206,18 +213,21 @@ static int boot_secondary(unsigned int cpu, struct task_struct *ts)
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ccount = get_ccount();
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while (!ccount);
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cpu_start_ccount = ccount;
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WRITE_ONCE(cpu_start_ccount, ccount);
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while (time_before(jiffies, timeout)) {
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do {
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/*
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* Pairs with the first two memws in the
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* .Lboot_secondary.
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*/
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mb();
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if (!cpu_start_ccount)
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break;
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}
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ccount = READ_ONCE(cpu_start_ccount);
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} while (ccount && time_before(jiffies, timeout));
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if (cpu_start_ccount) {
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if (ccount) {
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smp_call_function_single(0, mx_cpu_stop,
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(void *)cpu, 1);
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cpu_start_ccount = 0;
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(void *)cpu, 1);
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WRITE_ONCE(cpu_start_ccount, 0);
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return -EIO;
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}
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}
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@ -237,6 +247,7 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
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pr_debug("%s: Calling wakeup_secondary(cpu:%d, idle:%p, sp: %08lx)\n",
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__func__, cpu, idle, start_info.stack);
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init_completion(&cpu_running);
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ret = boot_secondary(cpu, idle);
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if (ret == 0) {
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wait_for_completion_timeout(&cpu_running,
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@ -298,8 +309,10 @@ void __cpu_die(unsigned int cpu)
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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while (time_before(jiffies, timeout)) {
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system_invalidate_dcache_range((unsigned long)&cpu_start_id,
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sizeof(cpu_start_id));
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if (cpu_start_id == -cpu) {
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sizeof(cpu_start_id));
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/* Pairs with the second memw in the cpu_restart */
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mb();
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if (READ_ONCE(cpu_start_id) == -cpu) {
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platform_cpu_kill(cpu);
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return;
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}
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@ -89,7 +89,7 @@ static int ccount_timer_shutdown(struct clock_event_device *evt)
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container_of(evt, struct ccount_timer, evt);
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if (timer->irq_enabled) {
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disable_irq(evt->irq);
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disable_irq_nosync(evt->irq);
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timer->irq_enabled = 0;
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}
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return 0;
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@ -71,14 +71,17 @@ static void xtensa_mx_irq_mask(struct irq_data *d)
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENG);
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} else {
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mask = __this_cpu_read(cached_irq_mask) & ~mask;
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__this_cpu_write(cached_irq_mask, mask);
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xtensa_set_sr(mask, intenable);
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
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if (ext_irq >= HW_IRQ_MX_BASE) {
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set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG);
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return;
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}
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}
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mask = __this_cpu_read(cached_irq_mask) & ~mask;
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__this_cpu_write(cached_irq_mask, mask);
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xtensa_set_sr(mask, intenable);
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}
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static void xtensa_mx_irq_unmask(struct irq_data *d)
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unsigned int mask = 1u << d->hwirq;
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if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE |
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) -
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HW_IRQ_MX_BASE), MIENGSET);
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} else {
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mask |= __this_cpu_read(cached_irq_mask);
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__this_cpu_write(cached_irq_mask, mask);
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xtensa_set_sr(mask, intenable);
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XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) {
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unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq);
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if (ext_irq >= HW_IRQ_MX_BASE) {
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set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET);
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return;
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}
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}
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mask |= __this_cpu_read(cached_irq_mask);
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__this_cpu_write(cached_irq_mask, mask);
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xtensa_set_sr(mask, intenable);
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}
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static void xtensa_mx_irq_enable(struct irq_data *d)
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@ -113,7 +119,11 @@ static void xtensa_mx_irq_ack(struct irq_data *d)
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static int xtensa_mx_irq_retrigger(struct irq_data *d)
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{
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xtensa_set_sr(1 << d->hwirq, intset);
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unsigned int mask = 1u << d->hwirq;
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if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
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return 0;
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xtensa_set_sr(mask, intset);
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return 1;
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}
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@ -70,7 +70,11 @@ static void xtensa_irq_ack(struct irq_data *d)
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static int xtensa_irq_retrigger(struct irq_data *d)
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{
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xtensa_set_sr(1 << d->hwirq, intset);
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unsigned int mask = 1u << d->hwirq;
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if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
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return 0;
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xtensa_set_sr(mask, intset);
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return 1;
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}
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