ARC: [plat-axs103] refactor the quad core DT quirk code
Refactor the quad core DT quirk code: get rid of waste division and multiplication by 1000000 constant. Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -317,19 +317,21 @@ static void __init axs103_early_init(void)
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* Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
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* of fudging the freq in DT
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*/
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#define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000
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unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
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if (num_cores > 2) {
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u32 freq = 50, orig;
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u32 freq;
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int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk");
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const struct fdt_property *prop;
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prop = fdt_get_property(initial_boot_params, off,
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"assigned-clock-rates", NULL);
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orig = be32_to_cpu(*(u32*)(prop->data)) / 1000000;
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freq = be32_to_cpu(*(u32 *)(prop->data));
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/* Patching .dtb in-place with new core clock value */
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if (freq != orig ) {
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freq = cpu_to_be32(freq * 1000000);
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if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) {
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freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ);
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fdt_setprop_inplace(initial_boot_params, off,
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"assigned-clock-rates", &freq, sizeof(freq));
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}
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