DMA mapping updates for 5.2
- remove the already broken support for NULL dev arguments to the DMA API calls - Kconfig tidyups -----BEGIN PGP SIGNATURE----- iQI/BAABCgApFiEEgdbnc3r/njty3Iq9D55TZVIEUYMFAlzT00YLHGhjaEBsc3Qu ZGUACgkQD55TZVIEUYO66hAAx2kCUIh+K2gFB5uxHqZiG62UmRjkPzolxcR5/Jx9 4Rz6NRAE+rp8v2fbBr2bveDx7cF5bm1L+pRyRsFMfwkm3a8dCHQ51ldIm5VFoI3e NiX6Zoxk02BCXP/Qk//aHeNW9dBmuiemiXzdPEhOvWvVzqTO5JZrECQpkHEkG+8A R/IWU15sr5xzw9Td/HVN9CRJri/qiTAuB9nSoP6BGjZeHkQjREJKNMGKDTvSzH4L tlyD1G7yEymQvLBqGGO64ztuav00l8sqjI3tn1mmwpw4VTajabeRHPnWh+7g9Od+ sH1pRvIOTvEMc456fizufYIOedB5Ze344kgfrxhngRbBVXmMfShr8ZLzdIUGhGjY 1cdGqIUOEKywiDf13KrHVkNU+lJtvjMCMxvV93mAYRLOIQg0Jf4T2kklgKyEhqrG rqFdbbtSBzmLjPyqc1FS0heDWmA+yJsKAumGcH4blJXCpsD1rHWGe0AJ34x+OHPT tw5l+P4zAH1eO1qHCtmxN9s0lXZv1VLcFkOrJH91LPvAhZsUCrdqDjyJpTUYaIao yzkiLbDwFO7SVoqzaVNlVZIJ/9LX0qfAnl2Atty+sAQomrQMoviNSzGbLSLQqhHN FbTIEBMxrxS49+3lfzHOS/lYPpJp6B31yotNM+6YpXmbRQZN5gjGNYBqhKD+7Rgn L0Y= =IdsP -----END PGP SIGNATURE----- Merge tag 'dma-mapping-5.2' of git://git.infradead.org/users/hch/dma-mapping Pull DMA mapping updates from Christoph Hellwig: - remove the already broken support for NULL dev arguments to the DMA API calls - Kconfig tidyups * tag 'dma-mapping-5.2' of git://git.infradead.org/users/hch/dma-mapping: dma-mapping: add a Kconfig symbol to indicate arch_dma_prep_coherent presence dma-mapping: remove an unnecessary NULL check x86/dma: Remove the x86_dma_fallback_dev hack dma-mapping: remove leftover NULL device support arm: use a dummy struct device for ISA DMA use of the DMA API pxa3xx-gcu: pass struct device to dma_mmap_coherent gbefb: switch to managed version of the DMA allocator da8xx-fb: pass struct device to DMA API functions parport_ip32: pass struct device to DMA API functions dma: select GENERIC_ALLOCATOR for DMA_REMAP
This commit is contained in:
commit
ddab5337b2
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@ -365,13 +365,12 @@ __get_free_pages() (but takes size instead of a page order). If your
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driver needs regions sized smaller than a page, you may prefer using
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the dma_pool interface, described below.
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The consistent DMA mapping interfaces, for non-NULL dev, will by
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default return a DMA address which is 32-bit addressable. Even if the
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device indicates (via DMA mask) that it may address the upper 32-bits,
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consistent allocation will only return > 32-bit addresses for DMA if
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the consistent DMA mask has been explicitly changed via
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dma_set_coherent_mask(). This is true of the dma_pool interface as
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well.
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The consistent DMA mapping interfaces, will by default return a DMA address
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which is 32-bit addressable. Even if the device indicates (via the DMA mask)
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that it may address the upper 32-bits, consistent allocation will only
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return > 32-bit addresses for DMA if the consistent DMA mask has been
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explicitly changed via dma_set_coherent_mask(). This is true of the
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dma_pool interface as well.
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dma_alloc_coherent() returns two values: the virtual address which you
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can use to access it from the CPU and dma_handle which you pass to the
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@ -55,6 +55,12 @@ static int isa_get_dma_residue(unsigned int chan, dma_t *dma)
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return chan < 4 ? count : (count << 1);
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}
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static struct device isa_dma_dev = {
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.init_name = "fallback device",
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.coherent_dma_mask = ~(dma_addr_t)0,
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.dma_mask = &isa_dma_dev.coherent_dma_mask,
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};
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static void isa_enable_dma(unsigned int chan, dma_t *dma)
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{
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if (dma->invalid) {
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@ -89,7 +95,7 @@ static void isa_enable_dma(unsigned int chan, dma_t *dma)
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dma->sg = &dma->buf;
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dma->sgcount = 1;
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dma->buf.length = dma->count;
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dma->buf.dma_address = dma_map_single(NULL,
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dma->buf.dma_address = dma_map_single(&isa_dma_dev,
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dma->addr, dma->count,
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direction);
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}
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@ -151,6 +151,12 @@ static void iomd_free_dma(unsigned int chan, dma_t *dma)
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free_irq(idma->irq, idma);
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}
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static struct device isa_dma_dev = {
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.init_name = "fallback device",
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.coherent_dma_mask = ~(dma_addr_t)0,
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.dma_mask = &isa_dma_dev.coherent_dma_mask,
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};
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static void iomd_enable_dma(unsigned int chan, dma_t *dma)
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{
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struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
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@ -168,7 +174,7 @@ static void iomd_enable_dma(unsigned int chan, dma_t *dma)
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idma->dma.sg = &idma->dma.buf;
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idma->dma.sgcount = 1;
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idma->dma.buf.length = idma->dma.count;
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idma->dma.buf.dma_address = dma_map_single(NULL,
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idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
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idma->dma.addr, idma->dma.count,
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idma->dma.dma_mode == DMA_MODE_READ ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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@ -13,6 +13,7 @@ config ARM64
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select ARCH_HAS_DEVMEM_IS_ALLOWED
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select ARCH_HAS_DMA_COHERENT_TO_PFN
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select ARCH_HAS_DMA_MMAP_PGPROT
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select ARCH_HAS_DMA_PREP_COHERENT
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select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
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select ARCH_HAS_ELF_RANDOMIZE
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select ARCH_HAS_FAST_MULTIPLIER
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@ -1,6 +1,7 @@
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config CSKY
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_DMA_PREP_COHERENT
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select ARCH_HAS_SYNC_DMA_FOR_CPU
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select ARCH_USE_BUILTIN_BSWAP
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@ -13,14 +13,7 @@
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#include <asm/swiotlb.h>
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#include <linux/dma-contiguous.h>
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#ifdef CONFIG_ISA
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(24)
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#else
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# define ISA_DMA_BIT_MASK DMA_BIT_MASK(32)
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#endif
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extern int iommu_merge;
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extern struct device x86_dma_fallback_dev;
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extern int panic_on_overflow;
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extern const struct dma_map_ops *dma_ops;
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@ -30,7 +23,4 @@ static inline const struct dma_map_ops *get_arch_dma_ops(struct bus_type *bus)
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return dma_ops;
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}
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bool arch_dma_alloc_attrs(struct device **dev);
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#define arch_dma_alloc_attrs arch_dma_alloc_attrs
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#endif
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@ -233,9 +233,6 @@ static dma_addr_t gart_map_page(struct device *dev, struct page *page,
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unsigned long bus;
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phys_addr_t paddr = page_to_phys(page) + offset;
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if (!dev)
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dev = &x86_dma_fallback_dev;
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if (!need_iommu(dev, paddr, size))
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return paddr;
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@ -392,9 +389,6 @@ static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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if (nents == 0)
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return 0;
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if (!dev)
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dev = &x86_dma_fallback_dev;
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out = 0;
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start = 0;
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start_sg = sg;
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@ -51,14 +51,6 @@ int iommu_pass_through __read_mostly;
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extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
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/* Dummy device used for NULL arguments (normally ISA). */
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struct device x86_dma_fallback_dev = {
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.init_name = "fallback device",
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.coherent_dma_mask = ISA_DMA_BIT_MASK,
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.dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
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};
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EXPORT_SYMBOL(x86_dma_fallback_dev);
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void __init pci_iommu_alloc(void)
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{
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struct iommu_table_entry *p;
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@ -77,18 +69,6 @@ void __init pci_iommu_alloc(void)
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}
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}
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bool arch_dma_alloc_attrs(struct device **dev)
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{
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if (!*dev)
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*dev = &x86_dma_fallback_dev;
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if (!is_device_dma_capable(*dev))
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return false;
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return true;
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}
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EXPORT_SYMBOL(arch_dma_alloc_attrs);
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/*
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* See <Documentation/x86/x86_64/boot-options.txt> for the iommu kernel
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* parameter documentation.
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@ -568,6 +568,7 @@ static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
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/**
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* parport_ip32_dma_start - begins a DMA transfer
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* @p: partport to work on
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* @dir: DMA direction: DMA_TO_DEVICE or DMA_FROM_DEVICE
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* @addr: pointer to data buffer
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* @count: buffer size
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@ -575,8 +576,8 @@ static irqreturn_t parport_ip32_merr_interrupt(int irq, void *dev_id)
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* Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
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* correctly balanced.
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*/
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static int parport_ip32_dma_start(enum dma_data_direction dir,
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void *addr, size_t count)
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static int parport_ip32_dma_start(struct parport *p,
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enum dma_data_direction dir, void *addr, size_t count)
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{
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unsigned int limit;
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u64 ctrl;
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@ -601,7 +602,7 @@ static int parport_ip32_dma_start(enum dma_data_direction dir,
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/* Prepare DMA pointers */
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parport_ip32_dma.dir = dir;
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parport_ip32_dma.buf = dma_map_single(NULL, addr, count, dir);
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parport_ip32_dma.buf = dma_map_single(&p->bus_dev, addr, count, dir);
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parport_ip32_dma.len = count;
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parport_ip32_dma.next = parport_ip32_dma.buf;
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parport_ip32_dma.left = parport_ip32_dma.len;
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@ -625,11 +626,12 @@ static int parport_ip32_dma_start(enum dma_data_direction dir,
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/**
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* parport_ip32_dma_stop - ends a running DMA transfer
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* @p: partport to work on
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*
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* Calls to parport_ip32_dma_start() and parport_ip32_dma_stop() must be
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* correctly balanced.
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*/
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static void parport_ip32_dma_stop(void)
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static void parport_ip32_dma_stop(struct parport *p)
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{
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u64 ctx_a;
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u64 ctx_b;
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@ -685,8 +687,8 @@ static void parport_ip32_dma_stop(void)
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enable_irq(MACEISA_PAR_CTXB_IRQ);
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parport_ip32_dma.irq_on = 1;
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dma_unmap_single(NULL, parport_ip32_dma.buf, parport_ip32_dma.len,
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parport_ip32_dma.dir);
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dma_unmap_single(&p->bus_dev, parport_ip32_dma.buf,
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parport_ip32_dma.len, parport_ip32_dma.dir);
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}
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/**
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@ -1445,7 +1447,7 @@ static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
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priv->irq_mode = PARPORT_IP32_IRQ_HERE;
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parport_ip32_dma_start(DMA_TO_DEVICE, (void *)buf, len);
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parport_ip32_dma_start(p, DMA_TO_DEVICE, (void *)buf, len);
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reinit_completion(&priv->irq_complete);
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parport_ip32_frob_econtrol(p, ECR_DMAEN | ECR_SERVINTR, ECR_DMAEN);
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@ -1461,7 +1463,7 @@ static size_t parport_ip32_fifo_write_block_dma(struct parport *p,
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if (ecr & ECR_SERVINTR)
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break; /* DMA transfer just finished */
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}
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parport_ip32_dma_stop();
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parport_ip32_dma_stop(p);
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written = len - parport_ip32_dma_get_residue();
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priv->irq_mode = PARPORT_IP32_IRQ_FWD;
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|
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@ -1097,9 +1097,9 @@ static int fb_remove(struct platform_device *dev)
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unregister_framebuffer(info);
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fb_dealloc_cmap(&info->cmap);
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dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
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dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base,
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par->p_palette_base);
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dma_free_coherent(NULL, par->vram_size, par->vram_virt,
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dma_free_coherent(par->dev, par->vram_size, par->vram_virt,
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par->vram_phys);
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pm_runtime_put_sync(&dev->dev);
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pm_runtime_disable(&dev->dev);
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|
@ -1425,7 +1425,7 @@ static int fb_probe(struct platform_device *device)
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par->vram_size = roundup(par->vram_size/8, ulcm);
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par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
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par->vram_virt = dma_alloc_coherent(NULL,
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par->vram_virt = dma_alloc_coherent(par->dev,
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par->vram_size,
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&par->vram_phys,
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GFP_KERNEL | GFP_DMA);
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|
@ -1446,7 +1446,7 @@ static int fb_probe(struct platform_device *device)
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da8xx_fb_fix.line_length - 1;
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||||
/* allocate palette buffer */
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par->v_palette_base = dma_alloc_coherent(NULL, PALETTE_SIZE,
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par->v_palette_base = dma_alloc_coherent(par->dev, PALETTE_SIZE,
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||||
&par->p_palette_base,
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||||
GFP_KERNEL | GFP_DMA);
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||||
if (!par->v_palette_base) {
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||||
|
@ -1532,11 +1532,12 @@ err_dealloc_cmap:
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|||
fb_dealloc_cmap(&da8xx_fb_info->cmap);
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||||
|
||||
err_release_pl_mem:
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||||
dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
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||||
dma_free_coherent(par->dev, PALETTE_SIZE, par->v_palette_base,
|
||||
par->p_palette_base);
|
||||
|
||||
err_release_fb_mem:
|
||||
dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
|
||||
dma_free_coherent(par->dev, par->vram_size, par->vram_virt,
|
||||
par->vram_phys);
|
||||
|
||||
err_release_fb:
|
||||
framebuffer_release(da8xx_fb_info);
|
||||
|
|
|
@ -1162,9 +1162,9 @@ static int gbefb_probe(struct platform_device *p_dev)
|
|||
}
|
||||
gbe_revision = gbe->ctrlstat & 15;
|
||||
|
||||
gbe_tiles.cpu =
|
||||
dma_alloc_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t),
|
||||
&gbe_tiles.dma, GFP_KERNEL);
|
||||
gbe_tiles.cpu = dmam_alloc_coherent(&p_dev->dev,
|
||||
GBE_TLB_SIZE * sizeof(uint16_t),
|
||||
&gbe_tiles.dma, GFP_KERNEL);
|
||||
if (!gbe_tiles.cpu) {
|
||||
printk(KERN_ERR "gbefb: couldn't allocate tiles table\n");
|
||||
ret = -ENOMEM;
|
||||
|
@ -1178,19 +1178,20 @@ static int gbefb_probe(struct platform_device *p_dev)
|
|||
if (!gbe_mem) {
|
||||
printk(KERN_ERR "gbefb: couldn't map framebuffer\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_tiles_free;
|
||||
goto out_release_mem_region;
|
||||
}
|
||||
|
||||
gbe_dma_addr = 0;
|
||||
} else {
|
||||
/* try to allocate memory with the classical allocator
|
||||
* this has high chance to fail on low memory machines */
|
||||
gbe_mem = dma_alloc_wc(NULL, gbe_mem_size, &gbe_dma_addr,
|
||||
GFP_KERNEL);
|
||||
gbe_mem = dmam_alloc_attrs(&p_dev->dev, gbe_mem_size,
|
||||
&gbe_dma_addr, GFP_KERNEL,
|
||||
DMA_ATTR_WRITE_COMBINE);
|
||||
if (!gbe_mem) {
|
||||
printk(KERN_ERR "gbefb: couldn't allocate framebuffer memory\n");
|
||||
ret = -ENOMEM;
|
||||
goto out_tiles_free;
|
||||
goto out_release_mem_region;
|
||||
}
|
||||
|
||||
gbe_mem_phys = (unsigned long) gbe_dma_addr;
|
||||
|
@ -1237,11 +1238,6 @@ static int gbefb_probe(struct platform_device *p_dev)
|
|||
|
||||
out_gbe_unmap:
|
||||
arch_phys_wc_del(par->wc_cookie);
|
||||
if (gbe_dma_addr)
|
||||
dma_free_wc(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys);
|
||||
out_tiles_free:
|
||||
dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t),
|
||||
(void *)gbe_tiles.cpu, gbe_tiles.dma);
|
||||
out_release_mem_region:
|
||||
release_mem_region(GBE_BASE, sizeof(struct sgi_gbe));
|
||||
out_release_framebuffer:
|
||||
|
@ -1258,10 +1254,6 @@ static int gbefb_remove(struct platform_device* p_dev)
|
|||
unregister_framebuffer(info);
|
||||
gbe_turn_off();
|
||||
arch_phys_wc_del(par->wc_cookie);
|
||||
if (gbe_dma_addr)
|
||||
dma_free_wc(NULL, gbe_mem_size, gbe_mem, gbe_mem_phys);
|
||||
dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t),
|
||||
(void *)gbe_tiles.cpu, gbe_tiles.dma);
|
||||
release_mem_region(GBE_BASE, sizeof(struct sgi_gbe));
|
||||
gbefb_remove_sysfs(&p_dev->dev);
|
||||
framebuffer_release(info);
|
||||
|
|
|
@ -96,6 +96,7 @@ struct pxa3xx_gcu_batch {
|
|||
};
|
||||
|
||||
struct pxa3xx_gcu_priv {
|
||||
struct device *dev;
|
||||
void __iomem *mmio_base;
|
||||
struct clk *clk;
|
||||
struct pxa3xx_gcu_shared *shared;
|
||||
|
@ -493,7 +494,7 @@ pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma)
|
|||
if (size != SHARED_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
return dma_mmap_coherent(NULL, vma,
|
||||
return dma_mmap_coherent(priv->dev, vma,
|
||||
priv->shared, priv->shared_phys, size);
|
||||
|
||||
case SHARED_SIZE >> PAGE_SHIFT:
|
||||
|
@ -670,6 +671,7 @@ static int pxa3xx_gcu_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, priv);
|
||||
priv->resource_mem = r;
|
||||
priv->dev = dev;
|
||||
pxa3xx_gcu_reset(priv);
|
||||
pxa3xx_gcu_init_debug_timer(priv);
|
||||
|
||||
|
|
|
@ -267,9 +267,9 @@ size_t dma_direct_max_mapping_size(struct device *dev);
|
|||
|
||||
static inline const struct dma_map_ops *get_dma_ops(struct device *dev)
|
||||
{
|
||||
if (dev && dev->dma_ops)
|
||||
if (dev->dma_ops)
|
||||
return dev->dma_ops;
|
||||
return get_arch_dma_ops(dev ? dev->bus : NULL);
|
||||
return get_arch_dma_ops(dev->bus);
|
||||
}
|
||||
|
||||
static inline void set_dma_ops(struct device *dev,
|
||||
|
@ -650,7 +650,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
|
|||
|
||||
static inline u64 dma_get_mask(struct device *dev)
|
||||
{
|
||||
if (dev && dev->dma_mask && *dev->dma_mask)
|
||||
if (dev->dma_mask && *dev->dma_mask)
|
||||
return *dev->dma_mask;
|
||||
return DMA_BIT_MASK(32);
|
||||
}
|
||||
|
|
|
@ -72,6 +72,12 @@ static inline void arch_sync_dma_for_cpu_all(struct device *dev)
|
|||
}
|
||||
#endif /* CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL */
|
||||
|
||||
#ifdef CONFIG_ARCH_HAS_DMA_PREP_COHERENT
|
||||
void arch_dma_prep_coherent(struct page *page, size_t size);
|
||||
#else
|
||||
static inline void arch_dma_prep_coherent(struct page *page, size_t size)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_ARCH_HAS_DMA_PREP_COHERENT */
|
||||
|
||||
#endif /* _LINUX_DMA_NONCOHERENT_H */
|
||||
|
|
|
@ -38,6 +38,9 @@ config ARCH_HAS_SYNC_DMA_FOR_CPU
|
|||
config ARCH_HAS_SYNC_DMA_FOR_CPU_ALL
|
||||
bool
|
||||
|
||||
config ARCH_HAS_DMA_PREP_COHERENT
|
||||
bool
|
||||
|
||||
config ARCH_HAS_DMA_COHERENT_TO_PFN
|
||||
bool
|
||||
|
||||
|
@ -57,6 +60,7 @@ config SWIOTLB
|
|||
|
||||
config DMA_REMAP
|
||||
depends on MMU
|
||||
select GENERIC_ALLOCATOR
|
||||
bool
|
||||
|
||||
config DMA_DIRECT_REMAP
|
||||
|
|
|
@ -311,7 +311,7 @@ static inline bool dma_direct_possible(struct device *dev, dma_addr_t dma_addr,
|
|||
size_t size)
|
||||
{
|
||||
return swiotlb_force != SWIOTLB_FORCE &&
|
||||
(!dev || dma_capable(dev, dma_addr, size));
|
||||
dma_capable(dev, dma_addr, size);
|
||||
}
|
||||
|
||||
dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
|
||||
|
|
|
@ -238,17 +238,13 @@ u64 dma_get_required_mask(struct device *dev)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(dma_get_required_mask);
|
||||
|
||||
#ifndef arch_dma_alloc_attrs
|
||||
#define arch_dma_alloc_attrs(dev) (true)
|
||||
#endif
|
||||
|
||||
void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
|
||||
gfp_t flag, unsigned long attrs)
|
||||
{
|
||||
const struct dma_map_ops *ops = get_dma_ops(dev);
|
||||
void *cpu_addr;
|
||||
|
||||
WARN_ON_ONCE(dev && !dev->coherent_dma_mask);
|
||||
WARN_ON_ONCE(!dev->coherent_dma_mask);
|
||||
|
||||
if (dma_alloc_from_dev_coherent(dev, size, dma_handle, &cpu_addr))
|
||||
return cpu_addr;
|
||||
|
@ -256,9 +252,6 @@ void *dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle,
|
|||
/* let the implementation decide on the zone to allocate from: */
|
||||
flag &= ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM);
|
||||
|
||||
if (!arch_dma_alloc_attrs(&dev))
|
||||
return NULL;
|
||||
|
||||
if (dma_is_direct(ops))
|
||||
cpu_addr = dma_direct_alloc(dev, size, dma_handle, flag, attrs);
|
||||
else if (ops->alloc)
|
||||
|
|
Loading…
Reference in a new issue