nds32: support hardware prefetcher
We add a config for user to enable or disable this feature. It can be used to control the hardware prefetch function. Signed-off-by: Nylon Chen <nylon7@andestech.com> Acked-by: Greentime Hu <greentime@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com>
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@ -177,6 +177,13 @@ config CACHE_L2
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Say Y here to enable L2 cache if your SoC are integrated with L2CC.
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If unsure, say N.
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config HW_PRE
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bool "Enable hardware prefetcher"
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default y
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help
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Say Y here to enable hardware prefetcher feature.
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Only when CPU_VER.REV >= 0x09 can support.
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menu "Memory configuration"
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choice
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@ -740,14 +740,20 @@
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#define N13MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
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#define N13MISC_CTL_offPTEPF 2 /* Disable HPTWK L2 PTE pefetch */
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#define N13MISC_CTL_offSP_SHADOW_EN 4 /* Enable shadow stack pointers */
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#define MISC_CTL_offHWPRE 11 /* Enable HardWare PREFETCH */
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/* bit 6, 9:31 reserved */
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#define N13MISC_CTL_makBTB ( 0x1 << N13MISC_CTL_offBTB )
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#define N13MISC_CTL_makRTP ( 0x1 << N13MISC_CTL_offRTP )
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#define N13MISC_CTL_makPTEPF ( 0x1 << N13MISC_CTL_offPTEPF )
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#define N13MISC_CTL_makSP_SHADOW_EN ( 0x1 << N13MISC_CTL_offSP_SHADOW_EN )
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#define MISC_CTL_makHWPRE_EN ( 0x1 << MISC_CTL_offHWPRE )
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#ifdef CONFIG_HW_PRE
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#define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN|MISC_CTL_makHWPRE_EN)
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#else
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#define MISC_init (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
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#endif
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/******************************************************************************
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* PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
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@ -151,7 +151,7 @@ _tlb:
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#endif
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mtsr $r3, $TLB_MISC
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mfsr $r0, $MISC_CTL ! Enable BTB and RTP and shadow sp
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mfsr $r0, $MISC_CTL ! Enable BTB, RTP, shadow sp, and HW_PRE
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ori $r0, $r0, #MISC_init
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mtsr $r0, $MISC_CTL
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@ -39,6 +39,7 @@
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#define HWCAP_FPU_DP 0x040000
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#define HWCAP_V2 0x080000
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#define HWCAP_DX_REGS 0x100000
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#define HWCAP_HWPRE 0x200000
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unsigned long cpu_id, cpu_rev, cpu_cfgid;
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bool has_fpu = false;
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@ -75,6 +76,7 @@ static const char *hwcap_str[] = {
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"fpu_dp",
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"v2",
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"dx_regs",
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"hw_pre",
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NULL,
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};
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@ -221,6 +223,11 @@ static void __init setup_cpuinfo(void)
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if (__nds32__mfsr(NDS32_SR_MSC_CFG) & MSC_CFG_mskL2C)
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elf_hwcap |= HWCAP_L2C;
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#ifdef CONFIG_HW_PRE
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if (__nds32__mfsr(NDS32_SR_MISC_CTL) & MISC_CTL_makHWPRE_EN)
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elf_hwcap |= HWCAP_HWPRE;
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#endif
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tmp = __nds32__mfsr(NDS32_SR_CACHE_CTL);
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if (!IS_ENABLED(CONFIG_CPU_DCACHE_DISABLE))
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tmp |= CACHE_CTL_mskDC_EN;
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