ARM: SoC fixes
This is a slightly larger batch of fixes that we've been sitting on a few -rcs. Most of them are simple oneliners, but there are two sets that are slightly larger and worth pointing out: - A set of patches to OMAP to deal with hwmod for RTC on am33xx (beaglebone SoC, among others). It's the only clock that ever has a valid offset of 0, so a new flag needed introduction once this problem was discovered. - A collection of CCI fixes for performance counters discovered once people started using it on X-Gene CPUs. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX0OnNAAoJEIwa5zzehBx3C80P/3Adca+87uQPI57AWJL7TIU3 i9YAf1povBg/u5PHn2XiNj2gBeYtDL6vKTbca9zDX/ezSPaGFAp1nPsUG3m4yKLG 0FjkNRan+FvFoi195TxANrBeYE39/ZNWJCsPn01+2Q2EsYnlCn9wsFglxTQGObsN MI2rgYVxabdJC8TO5WuGUdJEa9TynU65fdqdD+KR+DfA8yOyu9wZEmE1JuHprUCQ H2MYYHHFZD5Y41/Y/SvdDVprCOd8lq8Syt7Vk1O6pQKQSGgojgGn36YJeBIapnOy 4y1/FFqoRe5FwSbt934q/4P/QpHwnGvIFi0edS+Reb6/3gUWRchQ8Dt1I1C/2QoJ J+7KQKR4SBSiu6LnsP8gNOAqulpyGzwE2aHBVD1mpbPIynA7G5MfI1pEJw4nVvFQ rAlBmuVzjaysuhKAdM32fd34dVwQljDiqh4qWtk0hbgjyPpdxT7QjIwSCR6vfbzo toOKQ2eiIqF+syOAnXbpPSmtaURavxvBim4DEXQfVHUbFHVErZ5zHmwGWjDc5vLT WixQ62hilHc08pcalY31RF3k21GwBXBVDf6clQ/9TDCErlCAlpjyN0/4ZrRpcYwz NHpFdbBNLzW0VJ0gHtwb+Xz4qgcUneTxXDUTaU46MYRquML/uqXMFrkJUQEOq1h5 nPGe55ItupK8REaMCJv/ =8pPd -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "This is a slightly larger batch of fixes that we've been sitting on a few -rcs. Most of them are simple oneliners, but there are two sets that are slightly larger and worth pointing out: - A set of patches to OMAP to deal with hwmod for RTC on am33xx (beaglebone SoC, among others). It's the only clock that ever has a valid offset of 0, so a new flag needed introduction once this problem was discovered. - A collection of CCI fixes for performance counters discovered once people started using it on X-Gene CPUs" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) arm-cci: pmu: Fix typo in event name Revert "ARM: tegra: fix erroneous address in dts" ARM: dts: imx6qdl: Fix SPDIF regression ARM: imx6: add missing BM_CLPCR_BYPASS_PMIC_READY setting for imx6sx ARM: dts: imx7d-sdb: fix ti,x-plate-ohms property name ARM: dts: kirkwood: Fix PCIe label on OpenRD ARM: kirkwood: ib62x0: fix size of u-boot environment partition bus: arm-ccn: make event groups reliable bus: arm-ccn: fix hrtimer registration bus: arm-ccn: fix PMU interrupt flags ARM: tegra: Correct polarity for Tegra114 PMIC interrupt MAINTAINERS: add tree entry for ARM/UniPhier architecture ARM: sun5i: Fix typo in trip point temperature MAINTAINERS: Switch to kernel.org account for Krzysztof Kozlowski ARM: imx6ul: populates platform device at .init_machine bus: arm-ccn: Add missing event attribute exclusions for host/guest bus: arm-ccn: Correct required arguments for XP PMU events bus: arm-ccn: Fix XP watchpoint settings bitmask bus: arm-ccn: Do not attempt to configure XPs for cycle counter bus: arm-ccn: Fix PMU handling of MN ...
This commit is contained in:
commit
e8b3b45de8
1
.mailmap
1
.mailmap
|
@ -88,6 +88,7 @@ Kay Sievers <kay.sievers@vrfy.org>
|
|||
Kenneth W Chen <kenneth.w.chen@intel.com>
|
||||
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski@samsung.com>
|
||||
Krzysztof Kozlowski <krzk@kernel.org> <k.kozlowski.k@gmail.com>
|
||||
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
Leonid I Ananiev <leonid.i.ananiev@intel.com>
|
||||
|
|
|
@ -18,13 +18,17 @@ and config2 fields of the perf_event_attr structure. The "events"
|
|||
directory provides configuration templates for all documented
|
||||
events, that can be used with perf tool. For example "xp_valid_flit"
|
||||
is an equivalent of "type=0x8,event=0x4". Other parameters must be
|
||||
explicitly specified. For events originating from device, "node"
|
||||
defines its index. All crosspoint events require "xp" (index),
|
||||
"port" (device port number) and "vc" (virtual channel ID) and
|
||||
"dir" (direction). Watchpoints (special "event" value 0xfe) also
|
||||
require comparator values ("cmp_l" and "cmp_h") and "mask", being
|
||||
index of the comparator mask.
|
||||
explicitly specified.
|
||||
|
||||
For events originating from device, "node" defines its index.
|
||||
|
||||
Crosspoint PMU events require "xp" (index), "bus" (bus number)
|
||||
and "vc" (virtual channel ID).
|
||||
|
||||
Crosspoint watchpoint-based events (special "event" value 0xfe)
|
||||
require "xp" and "vc" as as above plus "port" (device port index),
|
||||
"dir" (transmit/receive direction), comparator values ("cmp_l"
|
||||
and "cmp_h") and "mask", being index of the comparator mask.
|
||||
Masks are defined separately from the event description
|
||||
(due to limited number of the config values) in the "cmp_mask"
|
||||
directory, with first 8 configurable by user and additional
|
||||
|
|
16
MAINTAINERS
16
MAINTAINERS
|
@ -1624,7 +1624,7 @@ N: rockchip
|
|||
|
||||
ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
|
||||
M: Kukjin Kim <kgene@kernel.org>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
@ -1831,6 +1831,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
|
|||
ARM/UNIPHIER ARCHITECTURE
|
||||
M: Masahiro Yamada <yamada.masahiro@socionext.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/uniphier*
|
||||
F: arch/arm/include/asm/hardware/cache-uniphier.h
|
||||
|
@ -7464,7 +7465,8 @@ F: Documentation/devicetree/bindings/sound/max9860.txt
|
|||
F: sound/soc/codecs/max9860.*
|
||||
|
||||
MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/power/max14577_charger.c
|
||||
|
@ -7480,7 +7482,8 @@ F: include/dt-bindings/*/*max77802.h
|
|||
|
||||
MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS
|
||||
M: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
F: drivers/*/max14577*.c
|
||||
|
@ -9246,7 +9249,7 @@ F: drivers/pinctrl/sh-pfc/
|
|||
|
||||
PIN CONTROLLER - SAMSUNG
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
|
||||
|
@ -10179,7 +10182,7 @@ S: Maintained
|
|||
F: drivers/platform/x86/samsung-laptop.c
|
||||
|
||||
SAMSUNG AUDIO (ASoC) DRIVERS
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Sangbeom Kim <sbkim73@samsung.com>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
|
@ -10194,7 +10197,8 @@ F: drivers/video/fbdev/s3c-fb.c
|
|||
|
||||
SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS
|
||||
M: Sangbeom Kim <sbkim73@samsung.com>
|
||||
M: Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
M: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Supported
|
||||
|
|
|
@ -226,7 +226,7 @@
|
|||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
ti,elm-id = <&elm>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -161,7 +161,7 @@
|
|||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
ti,elm-id = <&elm>;
|
||||
|
||||
/* MTD partition table */
|
||||
partition@0 {
|
||||
|
|
|
@ -197,7 +197,7 @@
|
|||
gpmc,wr-access-ns = <30>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
elm_id = <&elm>;
|
||||
ti,elm-id = <&elm>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
|
|
@ -390,12 +390,12 @@
|
|||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
label = "lan5";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
|
@ -405,12 +405,12 @@
|
|||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan5";
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
|
|
|
@ -447,14 +447,11 @@
|
|||
samsung,dw-mshc-ciu-div = <3>;
|
||||
samsung,dw-mshc-sdr-timing = <0 4>;
|
||||
samsung,dw-mshc-ddr-timing = <0 2>;
|
||||
samsung,dw-mshc-hs400-timing = <0 2>;
|
||||
samsung,read-strobe-delay = <90>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
|
||||
bus-width = <8>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
vmmc-supply = <&ldo20_reg>;
|
||||
vqmmc-supply = <&ldo11_reg>;
|
||||
};
|
||||
|
|
|
@ -243,7 +243,7 @@
|
|||
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
|
||||
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
|
||||
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
|
||||
<&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
|
||||
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
|
|
|
@ -64,7 +64,7 @@
|
|||
cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakup;
|
||||
wakeup-source;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -131,7 +131,7 @@
|
|||
ti,y-min = /bits/ 16 <0>;
|
||||
ti,y-max = /bits/ 16 <0>;
|
||||
ti,pressure-max = /bits/ 16 <0>;
|
||||
ti,x-plat-ohms = /bits/ 16 <400>;
|
||||
ti,x-plate-ohms = /bits/ 16 <400>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -113,7 +113,7 @@
|
|||
|
||||
partition@e0000 {
|
||||
label = "u-boot environment";
|
||||
reg = <0xe0000 0x100000>;
|
||||
reg = <0xe0000 0x20000>;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
|
|
|
@ -116,6 +116,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -35,10 +35,15 @@
|
|||
ranges = <0 0 0x00000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
|
@ -54,10 +59,6 @@
|
|||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
gpmc,device-width = <2>;
|
||||
|
||||
gpmc,page-burst-access-ns = <5>;
|
||||
gpmc,cycle2cycle-delay-ns = <50>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
|
|
|
@ -46,6 +46,7 @@
|
|||
linux,mtd-name = "micron,mt29f4g16abbda3w";
|
||||
nand-bus-width = <16>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
|
|
|
@ -223,7 +223,9 @@
|
|||
};
|
||||
|
||||
&gpmc {
|
||||
ranges = <0 0 0x00000000 0x20000000>;
|
||||
ranges = <0 0 0x30000000 0x1000000>, /* CS0 */
|
||||
<4 0 0x2b000000 0x1000000>, /* CS4 */
|
||||
<5 0 0x2c000000 0x1000000>; /* CS5 */
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
|
|
|
@ -55,8 +55,6 @@
|
|||
#include "omap-gpmc-smsc9221.dtsi"
|
||||
|
||||
&gpmc {
|
||||
ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
|
||||
|
||||
ethernet@gpmc {
|
||||
reg = <5 0 0xff>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
|
|
|
@ -27,8 +27,6 @@
|
|||
#include "omap-gpmc-smsc9221.dtsi"
|
||||
|
||||
&gpmc {
|
||||
ranges = <5 0 0x2c000000 0x1000000>; /* CS5 */
|
||||
|
||||
ethernet@gpmc {
|
||||
reg = <5 0 0xff>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
|
|
|
@ -15,9 +15,6 @@
|
|||
#include "omap-gpmc-smsc9221.dtsi"
|
||||
|
||||
&gpmc {
|
||||
ranges = <4 0 0x2b000000 0x1000000>, /* CS4 */
|
||||
<5 0 0x2c000000 0x1000000>; /* CS5 */
|
||||
|
||||
smsc1: ethernet@gpmc {
|
||||
reg = <5 0 0xff>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
|
|
|
@ -84,7 +84,7 @@
|
|||
trips {
|
||||
cpu_alert0: cpu_alert0 {
|
||||
/* milliCelsius */
|
||||
temperature = <850000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
|
|
@ -897,7 +897,7 @@
|
|||
palmas: tps65913@58 {
|
||||
compatible = "ti,palmas";
|
||||
reg = <0x58>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
|
@ -802,7 +802,7 @@
|
|||
palmas: pmic@58 {
|
||||
compatible = "ti,palmas";
|
||||
reg = <0x58>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
|
@ -63,7 +63,7 @@
|
|||
palmas: pmic@58 {
|
||||
compatible = "ti,palmas";
|
||||
reg = <0x58>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
|
@ -1382,7 +1382,7 @@
|
|||
* Pin 41: BR_UART1_TXD
|
||||
* Pin 44: BR_UART1_RXD
|
||||
*/
|
||||
serial@0,70006000 {
|
||||
serial@70006000 {
|
||||
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -1394,7 +1394,7 @@
|
|||
* Pin 71: UART2_CTS_L
|
||||
* Pin 74: UART2_RTS_L
|
||||
*/
|
||||
serial@0,70006040 {
|
||||
serial@70006040 {
|
||||
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -64,6 +64,7 @@ static void __init imx6ul_init_machine(void)
|
|||
if (parent == NULL)
|
||||
pr_warn("failed to initialize soc device\n");
|
||||
|
||||
of_platform_default_populate(NULL, NULL, parent);
|
||||
imx6ul_enet_init();
|
||||
imx_anatop_init();
|
||||
imx6ul_pm_init();
|
||||
|
|
|
@ -295,7 +295,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
|
|||
val &= ~BM_CLPCR_SBYOS;
|
||||
if (cpu_is_imx6sl())
|
||||
val |= BM_CLPCR_BYPASS_PMIC_READY;
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx())
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
|
||||
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
|
||||
else
|
||||
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
|
||||
|
@ -310,7 +310,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
|
|||
val |= 0x3 << BP_CLPCR_STBY_COUNT;
|
||||
val |= BM_CLPCR_VSTBY;
|
||||
val |= BM_CLPCR_SBYOS;
|
||||
if (cpu_is_imx6sl())
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx())
|
||||
val |= BM_CLPCR_BYPASS_PMIC_READY;
|
||||
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul())
|
||||
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
|
||||
|
|
|
@ -220,9 +220,6 @@ static int am33xx_cm_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
|
|||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout(_is_module_ready(inst, clkctrl_offs),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
||||
|
@ -246,9 +243,6 @@ static int am33xx_cm_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
|
|||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout((_clkctrl_idlest(inst, clkctrl_offs) ==
|
||||
CLKCTRL_IDLEST_DISABLED),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
|
|
@ -278,9 +278,6 @@ static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
|
|||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout(_is_module_ready(part, inst, clkctrl_offs),
|
||||
MAX_MODULE_READY_TIME, i);
|
||||
|
||||
|
@ -304,9 +301,6 @@ static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
|
|||
{
|
||||
int i = 0;
|
||||
|
||||
if (!clkctrl_offs)
|
||||
return 0;
|
||||
|
||||
omap_test_timeout((_clkctrl_idlest(part, inst, clkctrl_offs) ==
|
||||
CLKCTRL_IDLEST_DISABLED),
|
||||
MAX_MODULE_DISABLE_TIME, i);
|
||||
|
|
|
@ -1053,6 +1053,10 @@ static int _omap4_wait_target_disable(struct omap_hwmod *oh)
|
|||
if (oh->flags & HWMOD_NO_IDLEST)
|
||||
return 0;
|
||||
|
||||
if (!oh->prcm.omap4.clkctrl_offs &&
|
||||
!(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
|
||||
return 0;
|
||||
|
||||
return omap_cm_wait_module_idle(oh->clkdm->prcm_partition,
|
||||
oh->clkdm->cm_inst,
|
||||
oh->prcm.omap4.clkctrl_offs, 0);
|
||||
|
@ -2971,6 +2975,10 @@ static int _omap4_wait_target_ready(struct omap_hwmod *oh)
|
|||
if (!_find_mpu_rt_port(oh))
|
||||
return 0;
|
||||
|
||||
if (!oh->prcm.omap4.clkctrl_offs &&
|
||||
!(oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET))
|
||||
return 0;
|
||||
|
||||
/* XXX check module SIDLEMODE, hardreset status */
|
||||
|
||||
return omap_cm_wait_module_ready(oh->clkdm->prcm_partition,
|
||||
|
|
|
@ -443,8 +443,12 @@ struct omap_hwmod_omap2_prcm {
|
|||
* HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
|
||||
* module-level context loss register associated with them; this
|
||||
* flag bit should be set in those cases
|
||||
* HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET: Some IP blocks have a valid CLKCTRL
|
||||
* offset of zero; this flag bit should be set in those cases to
|
||||
* distinguish from hwmods that have no clkctrl offset.
|
||||
*/
|
||||
#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT (1 << 0)
|
||||
#define HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET (1 << 1)
|
||||
|
||||
/**
|
||||
* struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
|
||||
#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
|
||||
#define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
|
||||
#define PRCM_FLAGS(oh, flag) ((oh).prcm.omap4.flags = (flag))
|
||||
|
||||
/*
|
||||
* 'l3' class
|
||||
|
@ -1296,6 +1297,7 @@ static void omap_hwmod_am33xx_clkctrl(void)
|
|||
CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
|
||||
PRCM_FLAGS(am33xx_rtc_hwmod, HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
|
||||
CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
|
||||
|
|
|
@ -722,8 +722,20 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
|
|||
* display serial interface controller
|
||||
*/
|
||||
|
||||
static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
|
||||
.rev_offs = 0x0000,
|
||||
.sysc_offs = 0x0010,
|
||||
.syss_offs = 0x0014,
|
||||
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
||||
SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|
||||
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
||||
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
||||
.sysc_fields = &omap_hwmod_sysc_type1,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
|
||||
.name = "dsi",
|
||||
.sysc = &omap3xxx_dsi_sysc,
|
||||
};
|
||||
|
||||
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
|
||||
|
|
|
@ -551,7 +551,7 @@ static struct attribute *cci5xx_pmu_event_attrs[] = {
|
|||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),
|
||||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),
|
||||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),
|
||||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snopp_rq_stall_tt_full, 0xE),
|
||||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_stall_tt_full, 0xE),
|
||||
CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),
|
||||
NULL
|
||||
};
|
||||
|
|
|
@ -187,6 +187,7 @@ struct arm_ccn {
|
|||
struct arm_ccn_component *xp;
|
||||
|
||||
struct arm_ccn_dt dt;
|
||||
int mn_id;
|
||||
};
|
||||
|
||||
static DEFINE_MUTEX(arm_ccn_mutex);
|
||||
|
@ -212,6 +213,7 @@ static int arm_ccn_node_to_xp_port(int node)
|
|||
#define CCN_CONFIG_TYPE(_config) (((_config) >> 8) & 0xff)
|
||||
#define CCN_CONFIG_EVENT(_config) (((_config) >> 16) & 0xff)
|
||||
#define CCN_CONFIG_PORT(_config) (((_config) >> 24) & 0x3)
|
||||
#define CCN_CONFIG_BUS(_config) (((_config) >> 24) & 0x3)
|
||||
#define CCN_CONFIG_VC(_config) (((_config) >> 26) & 0x7)
|
||||
#define CCN_CONFIG_DIR(_config) (((_config) >> 29) & 0x1)
|
||||
#define CCN_CONFIG_MASK(_config) (((_config) >> 30) & 0xf)
|
||||
|
@ -241,6 +243,7 @@ static CCN_FORMAT_ATTR(xp, "config:0-7");
|
|||
static CCN_FORMAT_ATTR(type, "config:8-15");
|
||||
static CCN_FORMAT_ATTR(event, "config:16-23");
|
||||
static CCN_FORMAT_ATTR(port, "config:24-25");
|
||||
static CCN_FORMAT_ATTR(bus, "config:24-25");
|
||||
static CCN_FORMAT_ATTR(vc, "config:26-28");
|
||||
static CCN_FORMAT_ATTR(dir, "config:29-29");
|
||||
static CCN_FORMAT_ATTR(mask, "config:30-33");
|
||||
|
@ -253,6 +256,7 @@ static struct attribute *arm_ccn_pmu_format_attrs[] = {
|
|||
&arm_ccn_pmu_format_attr_type.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_event.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_port.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_bus.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_vc.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_dir.attr.attr,
|
||||
&arm_ccn_pmu_format_attr_mask.attr.attr,
|
||||
|
@ -328,6 +332,7 @@ struct arm_ccn_pmu_event {
|
|||
static ssize_t arm_ccn_pmu_event_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
|
||||
struct arm_ccn_pmu_event *event = container_of(attr,
|
||||
struct arm_ccn_pmu_event, attr);
|
||||
ssize_t res;
|
||||
|
@ -349,10 +354,17 @@ static ssize_t arm_ccn_pmu_event_show(struct device *dev,
|
|||
break;
|
||||
case CCN_TYPE_XP:
|
||||
res += snprintf(buf + res, PAGE_SIZE - res,
|
||||
",xp=?,port=?,vc=?,dir=?");
|
||||
",xp=?,vc=?");
|
||||
if (event->event == CCN_EVENT_WATCHPOINT)
|
||||
res += snprintf(buf + res, PAGE_SIZE - res,
|
||||
",cmp_l=?,cmp_h=?,mask=?");
|
||||
",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
|
||||
else
|
||||
res += snprintf(buf + res, PAGE_SIZE - res,
|
||||
",bus=?");
|
||||
|
||||
break;
|
||||
case CCN_TYPE_MN:
|
||||
res += snprintf(buf + res, PAGE_SIZE - res, ",node=%d", ccn->mn_id);
|
||||
break;
|
||||
default:
|
||||
res += snprintf(buf + res, PAGE_SIZE - res, ",node=?");
|
||||
|
@ -383,9 +395,9 @@ static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
|
|||
}
|
||||
|
||||
static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
|
||||
CCN_EVENT_MN(eobarrier, "dir=0,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_MN(ecbarrier, "dir=0,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_MN(dvmop, "dir=0,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
|
||||
CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
|
||||
CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
|
||||
CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
|
||||
|
@ -733,9 +745,10 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
|
|||
|
||||
if (has_branch_stack(event) || event->attr.exclude_user ||
|
||||
event->attr.exclude_kernel || event->attr.exclude_hv ||
|
||||
event->attr.exclude_idle) {
|
||||
event->attr.exclude_idle || event->attr.exclude_host ||
|
||||
event->attr.exclude_guest) {
|
||||
dev_warn(ccn->dev, "Can't exclude execution levels!\n");
|
||||
return -EOPNOTSUPP;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (event->cpu < 0) {
|
||||
|
@ -759,6 +772,12 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
|
|||
|
||||
/* Validate node/xp vs topology */
|
||||
switch (type) {
|
||||
case CCN_TYPE_MN:
|
||||
if (node_xp != ccn->mn_id) {
|
||||
dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case CCN_TYPE_XP:
|
||||
if (node_xp >= ccn->num_xps) {
|
||||
dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
|
||||
|
@ -886,6 +905,10 @@ static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
|
|||
struct arm_ccn_component *xp;
|
||||
u32 val, dt_cfg;
|
||||
|
||||
/* Nothing to do for cycle counter */
|
||||
if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
|
||||
return;
|
||||
|
||||
if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
|
||||
xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
|
||||
else
|
||||
|
@ -917,38 +940,17 @@ static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
|
|||
arm_ccn_pmu_read_counter(ccn, hw->idx));
|
||||
hw->state = 0;
|
||||
|
||||
/*
|
||||
* Pin the timer, so that the overflows are handled by the chosen
|
||||
* event->cpu (this is the same one as presented in "cpumask"
|
||||
* attribute).
|
||||
*/
|
||||
if (!ccn->irq)
|
||||
hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
|
||||
HRTIMER_MODE_REL_PINNED);
|
||||
|
||||
/* Set the DT bus input, engaging the counter */
|
||||
arm_ccn_pmu_xp_dt_config(event, 1);
|
||||
}
|
||||
|
||||
static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
|
||||
{
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
|
||||
struct hw_perf_event *hw = &event->hw;
|
||||
u64 timeout;
|
||||
|
||||
/* Disable counting, setting the DT bus to pass-through mode */
|
||||
arm_ccn_pmu_xp_dt_config(event, 0);
|
||||
|
||||
if (!ccn->irq)
|
||||
hrtimer_cancel(&ccn->dt.hrtimer);
|
||||
|
||||
/* Let the DT bus drain */
|
||||
timeout = arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) +
|
||||
ccn->num_xps;
|
||||
while (arm_ccn_pmu_read_counter(ccn, CCN_IDX_PMU_CYCLE_COUNTER) <
|
||||
timeout)
|
||||
cpu_relax();
|
||||
|
||||
if (flags & PERF_EF_UPDATE)
|
||||
arm_ccn_pmu_event_update(event);
|
||||
|
||||
|
@ -988,7 +990,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
|
|||
|
||||
/* Comparison values */
|
||||
writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
|
||||
writel((cmp_l >> 32) & 0xefffffff,
|
||||
writel((cmp_l >> 32) & 0x7fffffff,
|
||||
source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
|
||||
writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
|
||||
writel((cmp_h >> 32) & 0x0fffffff,
|
||||
|
@ -996,7 +998,7 @@ static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
|
|||
|
||||
/* Mask */
|
||||
writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
|
||||
writel((mask_l >> 32) & 0xefffffff,
|
||||
writel((mask_l >> 32) & 0x7fffffff,
|
||||
source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
|
||||
writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
|
||||
writel((mask_h >> 32) & 0x0fffffff,
|
||||
|
@ -1014,7 +1016,7 @@ static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
|
|||
hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
|
||||
|
||||
id = (CCN_CONFIG_VC(event->attr.config) << 4) |
|
||||
(CCN_CONFIG_PORT(event->attr.config) << 3) |
|
||||
(CCN_CONFIG_BUS(event->attr.config) << 3) |
|
||||
(CCN_CONFIG_EVENT(event->attr.config) << 0);
|
||||
|
||||
val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
|
||||
|
@ -1099,15 +1101,31 @@ static void arm_ccn_pmu_event_config(struct perf_event *event)
|
|||
spin_unlock(&ccn->dt.config_lock);
|
||||
}
|
||||
|
||||
static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
|
||||
{
|
||||
return bitmap_weight(ccn->dt.pmu_counters_mask,
|
||||
CCN_NUM_PMU_EVENT_COUNTERS + 1);
|
||||
}
|
||||
|
||||
static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
|
||||
{
|
||||
int err;
|
||||
struct hw_perf_event *hw = &event->hw;
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
|
||||
|
||||
err = arm_ccn_pmu_event_alloc(event);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/*
|
||||
* Pin the timer, so that the overflows are handled by the chosen
|
||||
* event->cpu (this is the same one as presented in "cpumask"
|
||||
* attribute).
|
||||
*/
|
||||
if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
|
||||
hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
|
||||
HRTIMER_MODE_REL_PINNED);
|
||||
|
||||
arm_ccn_pmu_event_config(event);
|
||||
|
||||
hw->state = PERF_HES_STOPPED;
|
||||
|
@ -1120,9 +1138,14 @@ static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
|
|||
|
||||
static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
|
||||
{
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
|
||||
|
||||
arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
|
||||
|
||||
arm_ccn_pmu_event_release(event);
|
||||
|
||||
if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
|
||||
hrtimer_cancel(&ccn->dt.hrtimer);
|
||||
}
|
||||
|
||||
static void arm_ccn_pmu_event_read(struct perf_event *event)
|
||||
|
@ -1130,6 +1153,24 @@ static void arm_ccn_pmu_event_read(struct perf_event *event)
|
|||
arm_ccn_pmu_event_update(event);
|
||||
}
|
||||
|
||||
static void arm_ccn_pmu_enable(struct pmu *pmu)
|
||||
{
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
|
||||
|
||||
u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
|
||||
val |= CCN_DT_PMCR__PMU_EN;
|
||||
writel(val, ccn->dt.base + CCN_DT_PMCR);
|
||||
}
|
||||
|
||||
static void arm_ccn_pmu_disable(struct pmu *pmu)
|
||||
{
|
||||
struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
|
||||
|
||||
u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
|
||||
val &= ~CCN_DT_PMCR__PMU_EN;
|
||||
writel(val, ccn->dt.base + CCN_DT_PMCR);
|
||||
}
|
||||
|
||||
static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
|
||||
{
|
||||
u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
|
||||
|
@ -1252,6 +1293,8 @@ static int arm_ccn_pmu_init(struct arm_ccn *ccn)
|
|||
.start = arm_ccn_pmu_event_start,
|
||||
.stop = arm_ccn_pmu_event_stop,
|
||||
.read = arm_ccn_pmu_event_read,
|
||||
.pmu_enable = arm_ccn_pmu_enable,
|
||||
.pmu_disable = arm_ccn_pmu_disable,
|
||||
};
|
||||
|
||||
/* No overflow interrupt? Have to use a timer instead. */
|
||||
|
@ -1361,6 +1404,8 @@ static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
|
|||
|
||||
switch (type) {
|
||||
case CCN_TYPE_MN:
|
||||
ccn->mn_id = id;
|
||||
return 0;
|
||||
case CCN_TYPE_DT:
|
||||
return 0;
|
||||
case CCN_TYPE_XP:
|
||||
|
@ -1471,8 +1516,9 @@ static int arm_ccn_probe(struct platform_device *pdev)
|
|||
/* Can set 'disable' bits, so can acknowledge interrupts */
|
||||
writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
|
||||
ccn->base + CCN_MN_ERRINT_STATUS);
|
||||
err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler, 0,
|
||||
dev_name(ccn->dev), ccn);
|
||||
err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
|
||||
IRQF_NOBALANCING | IRQF_NO_THREAD,
|
||||
dev_name(ccn->dev), ccn);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
|
@ -178,6 +178,7 @@ static int vexpress_config_populate(struct device_node *node)
|
|||
|
||||
parent = class_find_device(vexpress_config_class, NULL, bridge,
|
||||
vexpress_config_node_match);
|
||||
of_node_put(bridge);
|
||||
if (WARN_ON(!parent))
|
||||
return -ENODEV;
|
||||
|
||||
|
|
|
@ -709,9 +709,10 @@ static int scpi_probe(struct platform_device *pdev)
|
|||
struct mbox_client *cl = &pchan->cl;
|
||||
struct device_node *shmem = of_parse_phandle(np, "shmem", idx);
|
||||
|
||||
if (of_address_to_resource(shmem, 0, &res)) {
|
||||
ret = of_address_to_resource(shmem, 0, &res);
|
||||
of_node_put(shmem);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get SCPI payload mem resource\n");
|
||||
ret = -EINVAL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
|
|
|
@ -2185,7 +2185,7 @@ static int gpmc_probe_dt(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int gpmc_probe_dt_children(struct platform_device *pdev)
|
||||
static void gpmc_probe_dt_children(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct device_node *child;
|
||||
|
@ -2200,11 +2200,11 @@ static int gpmc_probe_dt_children(struct platform_device *pdev)
|
|||
else
|
||||
ret = gpmc_probe_generic_child(pdev, child);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
|
||||
child->name, ret);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
static int gpmc_probe_dt(struct platform_device *pdev)
|
||||
|
@ -2212,9 +2212,8 @@ static int gpmc_probe_dt(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int gpmc_probe_dt_children(struct platform_device *pdev)
|
||||
static void gpmc_probe_dt_children(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF */
|
||||
|
||||
|
@ -2369,16 +2368,10 @@ static int gpmc_probe(struct platform_device *pdev)
|
|||
goto setup_irq_failed;
|
||||
}
|
||||
|
||||
rc = gpmc_probe_dt_children(pdev);
|
||||
if (rc < 0) {
|
||||
dev_err(gpmc->dev, "failed to probe DT children\n");
|
||||
goto dt_children_failed;
|
||||
}
|
||||
gpmc_probe_dt_children(pdev);
|
||||
|
||||
return 0;
|
||||
|
||||
dt_children_failed:
|
||||
gpmc_free_irq(gpmc);
|
||||
setup_irq_failed:
|
||||
gpmc_gpio_exit(gpmc);
|
||||
gpio_init_failed:
|
||||
|
|
Loading…
Reference in a new issue