ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
Add the Altera Arria10 SPI Master Node in preparation for the A10SR MFD node. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
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@ -562,6 +562,21 @@
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status = "disabled";
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};
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spi1: spi@ffda5000 {
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compatible = "snps,dw-apb-ssi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xffda5000 0x100>;
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interrupts = <0 102 4>;
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num-chipselect = <4>;
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bus-num = <0>;
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/*32bit_access;*/
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tx-dma-channel = <&pdma 16>;
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rx-dma-channel = <&pdma 17>;
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clocks = <&spi_m_clk>;
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status = "disabled";
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};
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sdr: sdr@ffc25000 {
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compatible = "syscon";
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reg = <0xffcfb100 0x80>;
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