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Devicetree updates for v5.10: 

- Update dtc to upstream version v1.6.0-31-gcbca977ea121
 
 - dtx_diff help text reformatting
 
 - Speed-up validation time for binding and dtb checks using json for
   intermediate files
 
 - Add support for running yamllint on DT schema files
 
 - Remove old booting-without-of.rst
 
 - Extend the example schema to address common issues
 
 - Cleanup handling of additionalProperties/unevaluatedProperties
 
 - Ensure all DSI controller schemas reference dsi-controller.yaml
 
 - Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex, DFI,
   and Cisco Meraki
 
 - Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
   SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
   schema
 
 - Convert HiSilicon SoC and syscon bindings to DT schema
 
 - Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema
 
 - Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR,
    SATA, vf610 GPIO, and UART to DT schema
 
 - Add i.MX 8M compatible strings
 
 - Add LM81 and DS1780 as trivial devices
 
 - Various missing properties added to fix dtb validation warnings
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Merge tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:

 - Update dtc to upstream version v1.6.0-31-gcbca977ea121

 - dtx_diff help text reformatting

 - Speed-up validation time for binding and dtb checks using json for
   intermediate files

 - Add support for running yamllint on DT schema files

 - Remove old booting-without-of.rst

 - Extend the example schema to address common issues

 - Cleanup handling of additionalProperties/unevaluatedProperties

 - Ensure all DSI controller schemas reference dsi-controller.yaml

 - Vendor prefixes for Zealz, Wandbord/Technexion, Embest RIoT, Rex,
   DFI, and Cisco Meraki

 - Convert at25, SPMI bus, TI hwlock, HiSilicon Hi3660 USB3 PHY, Arm
   SP805 watchdog, Arm SP804, and Samsung 11-pin USB connector to DT
   schema

 - Convert HiSilicon SoC and syscon bindings to DT schema

 - Convert SiFive Risc-V L2 cache, PLIC, PRCI, and PWM to DT schema

 - Convert i.MX bindings for w1, crypto, rng, SIM, PM, DDR, SATA, vf610
   GPIO, and UART to DT schema

 - Add i.MX 8M compatible strings

 - Add LM81 and DS1780 as trivial devices

 - Various missing properties added to fix dtb validation warnings

* tag 'devicetree-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (111 commits)
  dt-bindings: misc: explicitly add #address-cells for slave mode
  spi: dt-bindings: spi-controller: explicitly require #address-cells=<0> for slave mode
  dt: Remove booting-without-of.rst
  dt-bindings: update usb-c-connector example
  dt-bindings: arm: hisilicon: add missing properties into cpuctrl.yaml
  dt-bindings: arm: hisilicon: add missing properties into sysctrl.yaml
  dt-bindings: pwm: imx: document i.MX compatibles
  scripts/dtc: Update to upstream version v1.6.0-31-gcbca977ea121
  dt-bindings: Add running yamllint to dt_binding_check
  dt-bindings: powerpc: Add a schema for the 'sleep' property
  dt-bindings: pinctrl: sirf: Fix typo abitrary
  dt-bindings: pinctrl: qcom: Fix typo abitrary
  dt-bindings: Explicitly allow additional properties in common schemas
  dt-bindings: Use 'additionalProperties' instead of 'unevaluatedProperties'
  dt-bindings: Add missing 'unevaluatedProperties'
  Docs: Fixing spelling errors in Documentation/devicetree/bindings/
  dt-bindings: arm: hisilicon: convert Hi6220 domain controller bindings to json-schema
  dt-bindings: riscv: convert pwm bindings to json-schema
  dt-bindings: riscv: convert plic bindings to json-schema
  dt-bindings: fu540: prci: convert PRCI bindings to json-schema
  ...
pull/193/head
Linus Torvalds 2020-10-14 15:31:58 -07:00
parent b4e1bce85f bd36e51d10
commit f888bdf982
432 changed files with 3774 additions and 3417 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/.gitignore vendored
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
*.example.dts
processed-schema*.yaml
processed-schema*.json

39
Documentation/devicetree/bindings/.yamllint 100644
View File

@ -0,0 +1,39 @@
extends: relaxed
rules:
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110
allow-non-breakable-words: true
level: warning
braces:
min-spaces-inside: 0
max-spaces-inside: 1
min-spaces-inside-empty: 0
max-spaces-inside-empty: 0
brackets:
min-spaces-inside: 0
max-spaces-inside: 1
min-spaces-inside-empty: 0
max-spaces-inside-empty: 0
colons: {max-spaces-before: 0, max-spaces-after: 1}
commas: {min-spaces-after: 1, max-spaces-after: 1}
comments:
require-starting-space: false
min-spaces-from-content: 1
comments-indentation: disable
document-start:
present: true
empty-lines:
max: 3
max-end: 1
empty-values:
forbid-in-block-mappings: true
forbid-in-flow-mappings: true
hyphens:
max-spaces-after: 1
indentation:
spaces: 2
indent-sequences: true
check-multi-line-strings: false
trailing-spaces: false

52
Documentation/devicetree/bindings/Makefile
View File

@ -3,7 +3,9 @@ DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_MIN_VERSION = 2020.5
DT_SCHEMA_LINT = $(shell which yamllint)
DT_SCHEMA_MIN_VERSION = 2020.8.1
PHONY += check_dtschema_version
check_dtschema_version:
@ -11,26 +13,40 @@ check_dtschema_version:
$(DT_DOC_CHECKER) --version 2>/dev/null || echo 0; } | sort -VC || \
{ echo "ERROR: dtschema minimum version is v$(DT_SCHEMA_MIN_VERSION)" >&2; false; }
quiet_cmd_chk_binding = CHKDT $(patsubst $(srctree)/%,%,$<)
cmd_chk_binding = $(DT_DOC_CHECKER) -u $(srctree)/$(src) $< ; \
$(DT_EXTRACT_EX) $< > $@
quiet_cmd_extract_ex = DTEX $@
cmd_extract_ex = $(DT_EXTRACT_EX) $< > $@
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
$(call if_changed,chk_binding)
$(call if_changed,extract_ex)
# Use full schemas when checking %.example.dts
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.yaml
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
find_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' ! \
-name '*.example.dt.yaml' \)
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = $(find_cmd) | \
xargs $(DT_SCHEMA_LINT) -f parsable -c $(srctree)/$(src)/.yamllint
quiet_cmd_chk_bindings = CHKDT $@
cmd_chk_bindings = $(find_cmd) | \
xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(srctree)/$(src)
quiet_cmd_mk_schema = SCHEMA $@
cmd_mk_schema = rm -f $@ ; \
cmd_mk_schema = f=$$(mktemp) ; \
$(if $(DT_MK_SCHEMA_FLAGS), \
echo $(real-prereqs), \
$(find_cmd)) | \
xargs $(DT_MK_SCHEMA) $(DT_MK_SCHEMA_FLAGS) >> $@
$(find_cmd)) > $$f ; \
$(DT_MK_SCHEMA) -j $(DT_MK_SCHEMA_FLAGS) @$$f > $@ ; \
rm -f $$f
define rule_chkdt
$(if $(DT_SCHEMA_LINT),$(call cmd,yamllint),)
$(call cmd,chk_bindings)
$(call cmd,mk_schema)
endef
DT_DOCS = $(shell $(find_cmd) | sed -e 's|^$(srctree)/||')
@ -39,33 +55,33 @@ override DTC_FLAGS := \
-Wno-graph_child_address \
-Wno-interrupt_provider
$(obj)/processed-schema-examples.yaml: $(DT_DOCS) check_dtschema_version FORCE
$(call if_changed,mk_schema)
$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
ifeq ($(DT_SCHEMA_FILES),)
# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
# Just copy processed-schema-examples.yaml
# Just copy processed-schema-examples.json
$(obj)/processed-schema.yaml: $(obj)/processed-schema-examples.yaml FORCE
$(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE
$(call if_changed,copy)
DT_SCHEMA_FILES = $(DT_DOCS)
else
# If DT_SCHEMA_FILES is specified, use it for processed-schema.yaml
# If DT_SCHEMA_FILES is specified, use it for processed-schema.json
$(obj)/processed-schema.yaml: DT_MK_SCHEMA_FLAGS := -u
$(obj)/processed-schema.yaml: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
$(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u
$(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
$(call if_changed,mk_schema)
endif
extra-$(CHECK_DT_BINDING) += processed-schema-examples.json
extra-$(CHECK_DTBS) += processed-schema.json
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
extra-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
extra-$(CHECK_DT_BINDING) += processed-schema-examples.yaml
extra-$(CHECK_DTBS) += processed-schema.yaml
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean

2
Documentation/devicetree/bindings/arm/actions.yaml
View File

@ -11,6 +11,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
# The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.

2
Documentation/devicetree/bindings/arm/altera.yaml
View File

@ -10,6 +10,8 @@ maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
$nodename:
const: "/"
compatible:
items:
- enum:

2
Documentation/devicetree/bindings/arm/axxia.yaml
View File

@ -10,6 +10,8 @@ maintainers:
- Anders Berg <anders.berg@lsi.com>
properties:
$nodename:
const: "/"
compatible:
description: LSI AXM5516 Validation board (Amarillo)
items:

2
Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
View File

@ -54,6 +54,8 @@ required:
- compatible
- mboxes
additionalProperties: false
examples:
- |
firmware {

2
Documentation/devicetree/bindings/arm/bitmain.yaml
View File

@ -10,6 +10,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
$nodename:
const: "/"
compatible:
items:
- enum:

2
Documentation/devicetree/bindings/arm/coresight-cti.yaml
View File

@ -220,6 +220,8 @@ then:
required:
- cpu
unevaluatedProperties: false
examples:
# minimum CTI definition. DEVID register used to set number of triggers.
- |

2
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@ -341,6 +341,8 @@ required:
dependencies:
rockchip,pmu: [enable-method]
additionalProperties: true
examples:
- |
cpus {

2
Documentation/devicetree/bindings/arm/digicolor.yaml
View File

@ -10,6 +10,8 @@ maintainers:
- Baruch Siach <baruch@tkos.co.il>
properties:
$nodename:
const: "/"
compatible:
const: cnxt,cx92755

23
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
View File

@ -1,23 +0,0 @@
Freescale i.MX7ULP Power Management Components
----------------------------------------------
The Multi-System Mode Controller (MSMC) is responsible for sequencing
the MCU into and out of all stop and run power modes. Specifically, it
monitors events to trigger transitions between power modes while
controlling the power, clocks, and memories of the MCU to achieve the
power consumption and functionality of that mode.
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
Standby modes for either Cortex family. Run, Wait, and Stop are the
common terms used for the primary operating modes of Kinetis
microcontrollers.
Required properties:
- compatible: Should be "fsl,imx7ulp-smc1".
- reg: Specifies base physical address and size of the register sets.
Example:
smc1: smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
};

42
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml 100644
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-pm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP Power Management Components
maintainers:
- A.s. Dong <aisheng.dong@nxp.com>
description: |
The Multi-System Mode Controller (MSMC) is responsible for sequencing
the MCU into and out of all stop and run power modes. Specifically, it
monitors events to trigger transitions between power modes while
controlling the power, clocks, and memories of the MCU to achieve the
power consumption and functionality of that mode.
The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
Standby modes for either Cortex family. Run, Wait, and Stop are the
common terms used for the primary operating modes of Kinetis
microcontrollers.
properties:
compatible:
const: fsl,imx7ulp-smc1
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
};

16
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.txt
View File

@ -1,16 +0,0 @@
Freescale i.MX7ULP System Integration Module
----------------------------------------------
The system integration module (SIM) provides system control and chip configuration
registers. In this module, chip revision information is located in JTAG ID register,
and a set of registers have been made available in DGO domain for SW use, with the
objective to maintain its value between system resets.
Required properties:
- compatible: Should be "fsl,imx7ulp-sim".
- reg: Specifies base physical address and size of the register sets.
Example:
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};

38
Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-sim.yaml 100644
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@ -0,0 +1,38 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/freescale/fsl,imx7ulp-sim.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP System Integration Module
maintainers:
- Anson Huang <anson.huang@nxp.com>
description: |
The system integration module (SIM) provides system control and chip configuration
registers. In this module, chip revision information is located in JTAG ID register,
and a set of registers have been made available in DGO domain for SW use, with the
objective to maintain its value between system resets.
properties:
compatible:
items:
- const: fsl,imx7ulp-sim
- const: syscon
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
};

54
Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml 100644
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@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon CPU controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
The clock registers and power registers of secondary cores are defined
in CPU controller, especially in HIX5HD2 SoC.
properties:
compatible:
items:
- const: hisilicon,cpuctrl
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
cpuctrl@a22000 {
compatible = "hisilicon,cpuctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x00a22000 0x2000>;
ranges = <0 0x00a22000 0x2000>;
clock: clock@0 {
compatible = "hisilicon,hix5hd2-clock";
reg = <0 0x2000>;
#clock-cells = <1>;
};
};
...

64
Documentation/devicetree/bindings/arm/hisilicon/controller/hi3798cv200-perictrl.yaml 100644
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@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi3798cv200-perictrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon Hi3798CV200 Peripheral Controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
The Hi3798CV200 Peripheral Controller controls peripherals, queries
their status, and configures some functions of peripherals.
properties:
compatible:
items:
- const: hisilicon,hi3798cv200-perictrl
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
additionalProperties:
type: object
examples:
- |
peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8a20000 0x1000>;
phy@850 {
compatible = "hisilicon,hi3798cv200-combphy";
reg = <0x850 0x8>;
#phy-cells = <1>;
clocks = <&crg 42>;
resets = <&crg 0x188 4>;
assigned-clocks = <&crg 42>;
assigned-clock-rates = <100000000>;
hisilicon,fixed-mode = <4>;
};
};
...

68
Documentation/devicetree/bindings/arm/hisilicon/controller/hi6220-domain-ctrl.yaml 100644
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/hi6220-domain-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon Hi6220 domain controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Hisilicon designs some special domain controllers for mobile platform,
such as: the power Always On domain controller, the Media domain
controller(e.g. codec, G3D ...) and the Power Management domain
controller.
The compatible names of each domain controller are as follows:
Power Always ON domain controller --> hisilicon,hi6220-aoctrl
Media domain controller --> hisilicon,hi6220-mediactrl
Power Management domain controller --> hisilicon,hi6220-pmctrl
properties:
compatible:
items:
- enum:
- hisilicon,hi6220-aoctrl
- hisilicon,hi6220-mediactrl
- hisilicon,hi6220-pmctrl
- const: syscon
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0xf7800000 0x2000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0xf4410000 0x1000>;
#clock-cells = <1>;
};
pm_ctrl@f7032000 {
compatible = "hisilicon,hi6220-pmctrl", "syscon";
reg = <0xf7032000 0x1000>;
#clock-cells = <1>;
};
...

34
Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-bootwrapper.yaml 100644
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@ -0,0 +1,34 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-bootwrapper.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Bootwrapper boot method
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: Bootwrapper boot method (software protocol on SMP)
properties:
compatible:
items:
- const: hisilicon,hip04-bootwrapper
boot-method:
description: |
Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size
minItems: 1
maxItems: 2
required:
- compatible
- boot-method
additionalProperties: false
...

27
Documentation/devicetree/bindings/arm/hisilicon/controller/hip04-fabric.yaml 100644
View File

@ -0,0 +1,27 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/hip04-fabric.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon Fabric controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: Hisilicon Fabric controller
properties:
compatible:
items:
- const: hisilicon,hip04-fabric
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
...

34
Documentation/devicetree/bindings/arm/hisilicon/controller/pctrl.yaml 100644
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@ -0,0 +1,34 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/pctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral misc control register
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: Peripheral misc control register
properties:
compatible:
items:
- const: hisilicon,pctrl
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
pctrl@fca09000 {
compatible = "hisilicon,pctrl";
reg = <0xfca09000 0x1000>;
};
...

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon system controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
The Hisilicon system controller is used on many Hisilicon boards, it can be
used to assist the slave core startup, reboot the system, etc.
There are some variants of the Hisilicon system controller, such as HiP01,
Hi3519, Hi6220 system controller, each of them is mostly compatible with the
Hisilicon system controller, but some same registers located at different
offset. In addition, the HiP01 system controller has some specific control
registers for HIP01 SoC family, such as slave core boot.
The compatible names of each system controller are as follows:
Hisilicon system controller --> hisilicon,sysctrl
HiP01 system controller --> hisilicon,hip01-sysctrl
Hi6220 system controller --> hisilicon,hi6220-sysctrl
Hi3519 system controller --> hisilicon,hi3519-sysctrl
allOf:
- if:
properties:
compatible:
contains:
const: hisilicon,hi6220-sysctrl
then:
required:
- '#clock-cells'
properties:
compatible:
oneOf:
- items:
- enum:
- hisilicon,sysctrl
- hisilicon,hi6220-sysctrl
- hisilicon,hi3519-sysctrl
- const: syscon
- items:
- const: hisilicon,hip01-sysctrl
- const: hisilicon,sysctrl
reg:
maxItems: 1
smp-offset:
description: |
offset in sysctrl for notifying slave cpu booting
cpu 1, reg;
cpu 2, reg + 0x4;
cpu 3, reg + 0x8;
If reg value is not zero, cpun exit wfi and go
$ref: /schemas/types.yaml#/definitions/uint32
resume-offset:
description: offset in sysctrl for notifying cpu0 when resume
$ref: /schemas/types.yaml#/definitions/uint32
reboot-offset:
description: offset in sysctrl for system reboot
$ref: /schemas/types.yaml#/definitions/uint32
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
/* Hisilicon system controller */
system-controller@802000 {
compatible = "hisilicon,sysctrl", "syscon";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
reg = <0x802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
clock: clock@0 {
compatible = "hisilicon,hi3620-clock";
reg = <0 0x10000>;
#clock-cells = <1>;
};
};
/* HiP01 system controller */
system-controller@10000000 {
compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
reg = <0x10000000 0x1000>;
reboot-offset = <0x4>;
};
/* Hi6220 system controller */
system-controller@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0xf7030000 0x2000>;
#clock-cells = <1>;
};
/* Hi3519 system controller */
system-controller@12010000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12010000 0x1000>;
};
...

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@ -1,14 +0,0 @@
* Hisilicon Hi3519 System Controller Block
This bindings use the following binding:
Documentation/devicetree/bindings/mfd/syscon.yaml
Required properties:
- compatible: "hisilicon,hi3519-sysctrl".
- reg: the register region of this block
Examples:
sysctrl: system-controller@12010000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12010000 0x1000>;
};

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@ -1,33 +0,0 @@
Hisilicon Hip06 Low Pin Count device
Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
Hip06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
Required properties:
- compatible: value should be as follows:
(a) "hisilicon,hip06-lpc"
(b) "hisilicon,hip07-lpc"
- #address-cells: must be 2 which stick to the ISA/EISA binding doc.
- #size-cells: must be 1 which stick to the ISA/EISA binding doc.
- reg: base memory range where the LPC register set is mapped.
Note:
The node name before '@' must be "isa" to represent the binding stick to the
ISA/EISA binding specification.
Example:
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xa01b0000 0x0 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};

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@ -1,319 +0,0 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi3660 SoC
Required root node properties:
- compatible = "hisilicon,hi3660";
HiKey960 Board
Required root node properties:
- compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
Hi3670 SoC
Required root node properties:
- compatible = "hisilicon,hi3670";
HiKey970 Board
Required root node properties:
- compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670";
Hi3798cv200 SoC
Required root node properties:
- compatible = "hisilicon,hi3798cv200";
Hi3798cv200 Poplar Board
Required root node properties:
- compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
Hi6220 SoC
Required root node properties:
- compatible = "hisilicon,hi6220";
HiKey Board
Required root node properties:
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
HiP01 ca9x2 Board
Required root node properties:
- compatible = "hisilicon,hip01-ca9x2";
HiP04 D01 Board
Required root node properties:
- compatible = "hisilicon,hip04-d01";
HiP05 D02 Board
Required root node properties:
- compatible = "hisilicon,hip05-d02";
HiP06 D03 Board
Required root node properties:
- compatible = "hisilicon,hip06-d03";
HiP07 D05 Board
Required root node properties:
- compatible = "hisilicon,hip07-d05";
Hisilicon system controller
Required properties:
- compatible : "hisilicon,sysctrl"
- reg : Register address and size
Optional properties:
- smp-offset : offset in sysctrl for notifying slave cpu booting
cpu 1, reg;
cpu 2, reg + 0x4;
cpu 3, reg + 0x8;
If reg value is not zero, cpun exit wfi and go
- resume-offset : offset in sysctrl for notifying cpu0 when resume
- reboot-offset : offset in sysctrl for system reboot
Example:
/* for Hi3620 */
sysctrl: system-controller@fc802000 {
compatible = "hisilicon,sysctrl";
reg = <0xfc802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon Hi3798CV200 Peripheral Controller
The Hi3798CV200 Peripheral Controller controls peripherals, queries
their status, and configures some functions of peripherals.
Required properties:
- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"
and "simple-mfd".
- reg: Register address and size of Peripheral Controller.
- #address-cells: Should be 1.
- #size-cells: Should be 1.
Examples:
perictrl: peripheral-controller@8a20000 {
compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
"simple-mfd";
reg = <0x8a20000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
-----------------------------------------------------------------------
Hisilicon Hi6220 system controller
Required properties:
- compatible : "hisilicon,hi6220-sysctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this controller as one of the system controllers,
its main functions are the same as Hisilicon system controller, but
the register offset of some core modules are different.
Example:
/*for Hi6220*/
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Power Always ON domain controller
Required properties:
- compatible : "hisilicon,hi6220-aoctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this system controller to control the power always
on domain for mobile platform.
Example:
/*for Hi6220*/
ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Media domain controller
Required properties:
- compatible : "hisilicon,hi6220-mediactrl"
- reg : Register address and size
- #clock-cells: should be set to 1, many clock registers are defined
under this controller and this property must be present.
Hisilicon designs this system controller to control the multimedia
domain(e.g. codec, G3D ...) for mobile platform.
Example:
/*for Hi6220*/
media_ctrl: media_ctrl@f4410000 {
compatible = "hisilicon,hi6220-mediactrl", "syscon";
reg = <0x0 0xf4410000 0x0 0x1000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 Power Management domain controller
Required properties:
- compatible : "hisilicon,hi6220-pmctrl"
- reg : Register address and size
- #clock-cells: should be set to 1, some clock registers are define
under this controller and this property must be present.
Hisilicon designs this system controller to control the power management
domain for mobile platform.
Example:
/*for Hi6220*/
pm_ctrl: pm_ctrl@f7032000 {
compatible = "hisilicon,hi6220-pmctrl", "syscon";
reg = <0x0 0xf7032000 0x0 0x1000>;
#clock-cells = <1>;
};
Hisilicon Hi6220 SRAM controller
Required properties:
- compatible : "hisilicon,hi6220-sramctrl", "syscon"
- reg : Register address and size
Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
SRAM banks for power management, modem, security, etc. Further, use "syscon"
managing the common sram which can be shared by multiple modules.
Example:
/*for Hi6220*/
sram: sram@fff80000 {
compatible = "hisilicon,hi6220-sramctrl", "syscon";
reg = <0x0 0xfff80000 0x0 0x12000>;
};
-----------------------------------------------------------------------
Hisilicon HiP01 system controller
Required properties:
- compatible : "hisilicon,hip01-sysctrl"
- reg : Register address and size
The HiP01 system controller is mostly compatible with hisilicon
system controller,but it has some specific control registers for
HIP01 SoC family, such as slave core boot, and also some same
registers located at different offset.
Example:
/* for hip01-ca9x2 */
sysctrl: system-controller@10000000 {
compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
reg = <0x10000000 0x1000>;
reboot-offset = <0x4>;
};
-----------------------------------------------------------------------
Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
Required properties:
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
- reg : Register address and size
The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 PCIe-SAS sub system */
pcie_sas: system_controller@b0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0xb0000000 0x10000>;
};
Hisilicon HiP05/HiP06 PERI sub system controller
Required properties:
- compatible : "hisilicon,peri-subctrl", "syscon";
- reg : Register address and size
The PERI sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
controllers include mdio, ddr, iic, uart, timer and so on.
Example:
/* for HiP05 sub peri system */
peri_c_subctrl: syscon@80000000 {
compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0x0 0x80000000 0x0 0x10000>;
};
Hisilicon HiP05/HiP06 DSA sub system controller
Required properties:
- compatible : "hisilicon,dsa-subctrl", "syscon";
- reg : Register address and size
The DSA sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 dsa sub system */
pcie_sas: system_controller@a0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0xa0000000 0x10000>;
};
-----------------------------------------------------------------------
Hisilicon CPU controller
Required properties:
- compatible : "hisilicon,cpuctrl"
- reg : Register address and size
The clock registers and power registers of secondary cores are defined
in CPU controller, especially in HIX5HD2 SoC.
-----------------------------------------------------------------------
PCTRL: Peripheral misc control register
Required Properties:
- compatible: "hisilicon,pctrl"
- reg: Address and size of pctrl.
Example:
/* for Hi3620 */
pctrl: pctrl@fca09000 {
compatible = "hisilicon,pctrl";
reg = <0xfca09000 0x1000>;
};
-----------------------------------------------------------------------
Fabric:
Required Properties:
- compatible: "hisilicon,hip04-fabric";
- reg: Address and size of Fabric
-----------------------------------------------------------------------
Bootwrapper boot method (software protocol on SMP):
Required Properties:
- compatible: "hisilicon,hip04-bootwrapper";
- boot-method: Address and size of boot method.
[0]: bootwrapper physical address
[1]: bootwrapper size
[2]: relocation physical address
[3]: relocation size

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@ -0,0 +1,67 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon Platforms Device Tree Bindings
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: Hi3660 based boards.
items:
- const: hisilicon,hi3660-hikey960
- const: hisilicon,hi3660
- description: Hi3670 based boards.
items:
- const: hisilicon,hi3670-hikey970
- const: hisilicon,hi3670
- description: Hi3798cv200 based boards.
items:
- const: hisilicon,hi3798cv200-poplar
- const: hisilicon,hi3798cv200
- description: Hi4511 Board
items:
- const: hisilicon,hi3620-hi4511
- description: Hi6220 based boards.
items:
- const: hisilicon,hi6220-hikey
- const: hisilicon,hi6220
- description: HiP01 based boards.
items:
- const: hisilicon,hip01-ca9x2
- const: hisilicon,hip01
- description: HiP04 D01 Board
items:
- const: hisilicon,hip04-d01
- description: HiP05 D02 Board
items:
- const: hisilicon,hip05-d02
- description: HiP06 D03 Board
items:
- const: hisilicon,hip06-d03
- description: HiP07 D05 Board
items:
- const: hisilicon,hip07-d05
- description: SD5203 based boards
items:
- const: H836ASDJ
- const: hisilicon,sd5203
...

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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon HiP06 Low Pin Count device
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
description: |
Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
provides I/O access to some legacy ISA devices.
HiP06 is based on arm64 architecture where there is no I/O space. So, the
I/O ports here are not CPU addresses, and there is no 'ranges' property in
LPC device node.
properties:
$nodename:
pattern: '^isa@[0-9a-f]+$'
description: |
The node name before '@' must be "isa" to represent the binding stick
to the ISA/EISA binding specification.
compatible:
enum:
- hisilicon,hip06-lpc
- hisilicon,hip07-lpc
reg:
maxItems: 1
'#address-cells':
const: 2
'#size-cells':
const: 1
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
isa@a01b0000 {
compatible = "hisilicon,hip06-lpc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0xa01b0000 0x1000>;
ipmi0: bt@e4 {
compatible = "ipmi-bt";
device_type = "ipmi";
reg = <0x01 0xe4 0x04>;
};
};
...

2
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View File

@ -10,6 +10,8 @@ maintainers:
- Linus Walleij <linus.walleij@linaro.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- items:

2
Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
View File

@ -47,6 +47,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
pericfg@10003000 {

2
Documentation/devicetree/bindings/arm/nvidia,tegra194-ccplex.yaml
View File

@ -30,6 +30,8 @@ properties:
Specifies the bpmp node that needs to be queried to get
operating point data for all CPUs.
additionalProperties: true
examples:
- |
cpus {

2
Documentation/devicetree/bindings/arm/pmu.yaml
View File

@ -93,4 +93,6 @@ properties:
required:
- compatible
additionalProperties: false
...

3
Documentation/devicetree/bindings/arm/primecell.yaml
View File

@ -33,4 +33,7 @@ properties:
contains:
const: apb_pclk
additionalItems: true
additionalProperties: true
...

2
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View File

@ -73,6 +73,8 @@ description: |
foundry 2.
properties:
$nodename:
const: "/"
compatible:
oneOf:
- items:

2
Documentation/devicetree/bindings/arm/rda.yaml
View File

@ -10,6 +10,8 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
properties:
$nodename:
const: "/"
compatible:
items:
- enum:

3
Documentation/devicetree/bindings/arm/samsung/pmu.yaml
View File

@ -45,6 +45,9 @@ properties:
reg:
maxItems: 1
assigned-clock-parents: true
assigned-clocks: true
'#clock-cells':
const: 1

2
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View File

@ -50,6 +50,8 @@ required:
- '#size-cells'
- dma-ranges
unevaluatedProperties: false
examples:
- |
mlahb: ahb@38000000 {

2
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View File

@ -10,6 +10,8 @@ maintainers:
- Alexandre Torgue <alexandre.torgue@st.com>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- items:

2
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -11,6 +11,8 @@ maintainers:
- Jonathan Hunter <jonathanh@nvidia.com>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- items:

2
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
View File

@ -308,6 +308,8 @@ required:
- clocks
- '#clock-cells'
additionalProperties: false
dependencies:
"nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
"nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]

2
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View File

@ -64,6 +64,8 @@ allOf:
required:
- sata
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

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@ -1,37 +0,0 @@
* Freescale i.MX AHCI SATA Controller
The Freescale i.MX SATA controller mostly conforms to the AHCI interface
with some special extensions at integration level.
Required properties:
- compatible : should be one of the following:
- "fsl,imx53-ahci" for i.MX53 SATA controller
- "fsl,imx6q-ahci" for i.MX6Q SATA controller
- "fsl,imx6qp-ahci" for i.MX6QP SATA controller
- interrupts : interrupt mapping for SATA IRQ
- reg : registers mapping
- clocks : list of clock specifiers, must contain an entry for each
required entry in clock-names
- clock-names : should include "sata", "sata_ref" and "ahb" entries
Optional properties:
- fsl,transmit-level-mV : transmit voltage level, in millivolts.
- fsl,transmit-boost-mdB : transmit boost level, in milli-decibels
- fsl,transmit-atten-16ths : transmit attenuation, in 16ths
- fsl,receive-eq-mdB : receive equalisation, in milli-decibels
Please refer to the technical documentation or the driver source code
for the list of legal values for these options.
- fsl,no-spread-spectrum : disable spread-spectrum clocking on the SATA
link.
Examples:
sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SATA>,
<&clks IMX6QDL_CLK_SATA_REF_100M>,
<&clks IMX6QDL_CLK_AHB>;
clock-names = "sata", "sata_ref", "ahb";
};

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@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX AHCI SATA Controller
maintainers:
- Shawn Guo <shawn.guo@linaro.org>
description: |
The Freescale i.MX SATA controller mostly conforms to the AHCI interface
with some special extensions at integration level.
properties:
compatible:
enum:
- fsl,imx53-ahci
- fsl,imx6q-ahci
- fsl,imx6qp-ahci
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: sata clock
- description: sata reference clock
- description: ahb clock
clock-names:
items:
- const: sata
- const: sata_ref
- const: ahb
fsl,transmit-level-mV:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit voltage level, in millivolts.
fsl,transmit-boost-mdB:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit boost level, in milli-decibels.
fsl,transmit-atten-16ths:
$ref: /schemas/types.yaml#/definitions/uint32
description: transmit attenuation, in 16ths.
fsl,receive-eq-mdB:
$ref: /schemas/types.yaml#/definitions/uint32
description: receive equalisation, in milli-decibels.
fsl,no-spread-spectrum:
$ref: /schemas/types.yaml#/definitions/flag
description: if present, disable spread-spectrum clocking on the SATA link.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
sata@2200000 {
compatible = "fsl,imx6q-ahci";
reg = <0x02200000 0x4000>;
interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_SATA>,
<&clks IMX6QDL_CLK_SATA_REF_100M>,
<&clks IMX6QDL_CLK_AHB>;
clock-names = "sata", "sata_ref", "ahb";
};

2
Documentation/devicetree/bindings/ata/pata-common.yaml
View File

@ -47,4 +47,6 @@ patternProperties:
The ID number of the drive port, 0 for the master port and 1 for the
slave port.
additionalProperties: true
...

2
Documentation/devicetree/bindings/ata/sata-common.yaml
View File

@ -47,4 +47,6 @@ patternProperties:
multiplier making it possible to connect up to 15 disks to a single
SATA port.
additionalProperties: true
...

2
Documentation/devicetree/bindings/bus/mti,mips-cdmm.yaml
View File

@ -26,6 +26,8 @@ required:
- compatible
- reg
additionalProperties: false
examples:
- |
cdmm@1bde8000 {

2
Documentation/devicetree/bindings/bus/renesas,bsc.yaml
View File

@ -44,6 +44,8 @@ properties:
required:
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

2
Documentation/devicetree/bindings/bus/simple-pm-bus.yaml
View File

@ -61,6 +61,8 @@ anyOf:
- required:
- power-domains
additionalProperties: true
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>

7
Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml
View File

@ -57,6 +57,11 @@ properties:
"ranges" property should provide a "reasonable" default that is known to
work. The software should initialize the bus controller according to it.
patternProperties:
"^.*@[1-5],[1-9a-f][0-9a-f]+$":
description: Devices attached to chip selects
type: object
required:
- compatible
- reg
@ -64,6 +69,8 @@ required:
- "#size-cells"
- ranges
additionalProperties: false
examples:
- |
// In this example,

2
Documentation/devicetree/bindings/chrome/google,cros-ec-typec.yaml
View File

@ -26,6 +26,8 @@ properties:
required:
- compatible
additionalProperties: true #fixme
examples:
- |+
spi0 {

2
Documentation/devicetree/bindings/clock/arm,syscon-icst.yaml
View File

@ -89,6 +89,8 @@ required:
- compatible
- clocks
additionalProperties: false
examples:
- |
vco1: clock {

6
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
View File

@ -134,7 +134,11 @@ properties:
"#reset-cells":
const: 1
unevaluatedProperties: false
clocks: true
clock-names: true
additionalProperties: false
required:
- compatible

2
Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
View File

@ -101,7 +101,7 @@ properties:
clock-names:
const: ref_clk
unevaluatedProperties: false
additionalProperties: false
required:
- compatible

20
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
View File

@ -50,6 +50,15 @@ properties:
'#clock-cells':
const: 1
clock-names:
minItems: 1
maxItems: 2
items:
enum: [ xin, clkin ]
clocks:
minItems: 1
maxItems: 2
patternProperties:
"^OUT[1-4]$":
type: object
@ -93,19 +102,12 @@ allOf:
maxItems: 1
else:
# Devices without builtin crystal
properties:
clock-names:
minItems: 1
maxItems: 2
items:
enum: [ xin, clkin ]
clocks:
minItems: 1
maxItems: 2
required:
- clock-names
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clk/versaclock.h>

4
Documentation/devicetree/bindings/clock/imx23-clock.yaml
View File

@ -87,6 +87,8 @@ examples:
serial@8006c000 {
compatible = "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
interrupts = <24>;
clocks = <&clks 32>;
dmas = <&dma_apbx 6>, <&dma_apbx 7>;
dma-names = "rx", "tx";
};

6
Documentation/devicetree/bindings/clock/imx28-clock.yaml
View File

@ -108,8 +108,10 @@ examples:
};
serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
compatible = "fsl,imx28-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
};

2
Documentation/devicetree/bindings/clock/imx6q-clock.yaml
View File

@ -57,6 +57,8 @@ required:
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/imx6sl-clock.yaml
View File

@ -33,6 +33,8 @@ required:
- interrupts
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/imx6sll-clock.yaml
View File

@ -49,6 +49,8 @@ required:
- clocks
- clock-names
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/imx6sx-clock.yaml
View File

@ -53,6 +53,8 @@ required:
- clocks
- clock-names
additionalProperties: false
examples:
# Clock Control Module node:
- |

2
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
View File

@ -49,6 +49,8 @@ required:
- clocks
- clock-names
additionalProperties: false
examples:
# Clock Control Module node:
- |

125
Documentation/devicetree/bindings/clock/imx8m-clock.yaml 100644
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@ -0,0 +1,125 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Family Clock Control Module Binding
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description: |
NXP i.MX8M Mini/Nano/Plus/Quad clock control module is an integrated clock
controller, which generates and supplies to all modules.
properties:
compatible:
enum:
- fsl,imx8mm-ccm
- fsl,imx8mn-ccm
- fsl,imx8mp-ccm
- fsl,imx8mq-ccm
reg:
maxItems: 1
clocks:
minItems: 6
maxItems: 7
clock-names:
minItems: 6
maxItems: 7
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h
for the full list of i.MX8M clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8mq-ccm
then:
properties:
clocks:
minItems: 7
maxItems: 7
items:
- description: 32k osc
- description: 25m osc
- description: 27m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
minItems: 7
maxItems: 7
items:
- const: ckil
- const: osc_25m
- const: osc_27m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
else:
properties:
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
items:
- const: osc_32k
- const: osc_24m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
additionalProperties: false
examples:
# Clock Control Module node:
- |
clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
};
- |
clock-controller@30390000 {
compatible = "fsl,imx8mq-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc_25m>, <&osc_27m>, <&clk_ext1>,
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
clock-names = "ckil", "osc_25m", "osc_27m", "clk_ext1",
"clk_ext2", "clk_ext3", "clk_ext4";
};
...

68
Documentation/devicetree/bindings/clock/imx8mm-clock.yaml
View File

@ -1,68 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8mm-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Mini Clock Control Module Binding
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description: |
NXP i.MX8M Mini clock control module is an integrated clock controller, which
generates and supplies to all modules.
properties:
compatible:
const: fsl,imx8mm-ccm
reg:
maxItems: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
items:
- const: osc_32k
- const: osc_24m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mm-clock.h
for the full list of i.MX8M Mini clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
examples:
# Clock Control Module node:
- |
clk: clock-controller@30380000 {
compatible = "fsl,imx8mm-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
};
...

70
Documentation/devicetree/bindings/clock/imx8mn-clock.yaml
View File

@ -1,70 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8mn-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Nano Clock Control Module Binding
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description: |
NXP i.MX8M Nano clock control module is an integrated clock controller, which
generates and supplies to all modules.
properties:
compatible:
const: fsl,imx8mn-ccm
reg:
maxItems: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
items:
- const: osc_32k
- const: osc_24m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mn-clock.h
for the full list of i.MX8M Nano clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |
clk: clock-controller@30380000 {
compatible = "fsl,imx8mn-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1",
"clk_ext2", "clk_ext3", "clk_ext4";
};
...

70
Documentation/devicetree/bindings/clock/imx8mp-clock.yaml
View File

@ -1,70 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8mp-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Plus Clock Control Module Binding
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description:
NXP i.MX8M Plus clock control module is an integrated clock controller, which
generates and supplies to all modules.
properties:
compatible:
const: fsl,imx8mp-ccm
reg:
maxItems: 1
clocks:
items:
- description: 32k osc
- description: 24m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
items:
- const: osc_32k
- const: osc_24m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
for the full list of i.MX8M Plus clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
# Clock Control Module node:
- |
clk: clock-controller@30380000 {
compatible = "fsl,imx8mp-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>,
<&clk_ext2>, <&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1",
"clk_ext2", "clk_ext3", "clk_ext4";
};
...

72
Documentation/devicetree/bindings/clock/imx8mq-clock.yaml
View File

@ -1,72 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8mq-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8M Quad Clock Control Module Binding
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description: |
NXP i.MX8M Quad clock control module is an integrated clock controller, which
generates and supplies to all modules.
properties:
compatible:
const: fsl,imx8mq-ccm
reg:
maxItems: 1
clocks:
items:
- description: 32k osc
- description: 25m osc
- description: 27m osc
- description: ext1 clock input
- description: ext2 clock input
- description: ext3 clock input
- description: ext4 clock input
clock-names:
items:
- const: ckil
- const: osc_25m
- const: osc_27m
- const: clk_ext1
- const: clk_ext2
- const: clk_ext3
- const: clk_ext4
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mq-clock.h
for the full list of i.MX8M Quad clock IDs.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
examples:
# Clock Control Module node:
- |
clk: clock-controller@30380000 {
compatible = "fsl,imx8mq-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
<&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
};
...

2
Documentation/devicetree/bindings/clock/intel,cgu-lgm.yaml
View File

@ -33,6 +33,8 @@ required:
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
cgu: clock-controller@e0200000 {

2
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View File

@ -56,6 +56,8 @@ required:
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

46
Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
View File

@ -1,46 +0,0 @@
SiFive FU540 PRCI bindings
On the FU540 family of SoCs, most system-wide clock and reset integration
is via the PRCI IP block.
Required properties:
- compatible: Should be "sifive,<chip>-prci". Only one value is
supported: "sifive,fu540-c000-prci"
- reg: Should describe the PRCI's register target physical address region
- clocks: Should point to the hfclk device tree node and the rtcclk
device tree node. The RTC clock here is not a time-of-day clock,
but is instead a high-stability clock source for system timers
and cycle counters.
- #clock-cells: Should be <1>
The clock consumer should specify the desired clock via the clock ID
macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
These macros begin with PRCI_CLK_.
The hfclk and rtcclk nodes are required, and represent physical
crystals or resonators located on the PCB. These nodes should be present
underneath /, rather than /soc.
Examples:
/* under /, in PCB-specific DT data */
hfclk: hfclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <33333333>;
clock-output-names = "hfclk";
};
rtcclk: rtcclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <1000000>;
clock-output-names = "rtcclk";
};
/* under /soc, in SoC-specific DT data */
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
reg = <0x0 0x10000000 0x0 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
};

60
Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml 100644
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
maintainers:
- Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
On the FU540 family of SoCs, most system-wide clock and reset integration
is via the PRCI IP block.
The clock consumer should specify the desired clock via the clock ID
macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
These macros begin with PRCI_CLK_.
The hfclk and rtcclk nodes are required, and represent physical
crystals or resonators located on the PCB. These nodes should be present
underneath /, rather than /soc.
properties:
compatible:
const: sifive,fu540-c000-prci
reg:
maxItems: 1
clocks:
items:
- description: high frequency clock.
- description: RTL clock.
clock-names:
items:
- const: hfclk
- const: rtcclk
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
reg = <0x10000000 0x1000>;
clocks = <&hfclk>, <&rtcclk>;
#clock-cells = <1>;
};

2
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
View File

@ -73,6 +73,8 @@ else:
The 'reg' property for the clock node is also required if there is a sub
range of registers for the clocks.
additionalProperties: false
examples:
- |
ap_clk: clock-controller@21500000 {

2
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
View File

@ -26,6 +26,8 @@ required:
- "#clock-cells"
- reg
additionalProperties: false
examples:
- |
ehrpwm_tbclk: syscon@4140 {

49
Documentation/devicetree/bindings/connector/samsung,usb-connector-11pin.txt
View File

@ -1,49 +0,0 @@
Samsung micro-USB 11-pin connector
==================================
Samsung micro-USB 11-pin connector is an extension of micro-USB connector.
It is present in multiple Samsung mobile devices.
It has additional pins to route MHL traffic simultanously with USB.
The bindings are superset of usb-connector bindings for micro-USB connector[1].
Required properties:
- compatible: must be: "samsung,usb-connector-11pin", "usb-b-connector",
- type: must be "micro".
Required nodes:
- any data bus to the connector should be modeled using the OF graph bindings
specified in bindings/graph.txt, unless the bus is between parent node and
the connector. Since single connector can have multpile data buses every bus
has assigned OF graph port number as follows:
0: High Speed (HS),
3: Mobile High-Definition Link (MHL), specific to 11-pin Samsung micro-USB.
[1]: bindings/connector/usb-connector.yaml
Example
-------
Micro-USB connector with HS lines routed via controller (MUIC) and MHL lines
connected to HDMI-MHL bridge (sii8620):
muic-max77843@66 {
...
usb_con: connector {
compatible = "samsung,usb-connector-11pin", "usb-b-connector";
label = "micro-USB";
type = "micro";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@3 {
reg = <3>;
usb_con_mhl: endpoint {
remote-endpoint = <&sii8620_mhl>;
};
};
};
};
};

76
Documentation/devicetree/bindings/connector/usb-connector.yaml
View File

@ -11,7 +11,8 @@ maintainers:
description:
A USB connector node represents a physical USB connector. It should be a child
of a USB interface controller.
of a USB interface controller or a separate node when it is attached to both
MUX and USB interface controller.
properties:
compatible:
@ -25,6 +26,10 @@ properties:
- const: gpio-usb-b-connector
- const: usb-b-connector
- items:
- const: samsung,usb-connector-11pin
- const: usb-b-connector
label:
description: Symbolic name for the connector.
@ -158,6 +163,18 @@ allOf:
- required:
- id-gpios
- if:
properties:
compatible:
contains:
const: samsung,usb-connector-11pin
then:
properties:
type:
const: micro
additionalProperties: true
examples:
# Micro-USB connector with HS lines routed via controller (MUIC).
- |
@ -221,6 +238,33 @@ examples:
};
};
# USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
# with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
# the output of MUX is connected to the SoC.
- |
connector {
compatible = "usb-c-connector";
label = "USB-C";
data-role = "dual";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hs_ep: endpoint {
remote-endpoint = <&usb3_hs_ep>;
};
};
port@1 {
reg = <1>;
ss_ep: endpoint {
remote-endpoint = <&hd3ss3220_in_ep>;
};
};
};
};
# USB connector with GPIO control lines
- |
#include <dt-bindings/gpio/gpio.h>
@ -233,3 +277,33 @@ examples:
vbus-supply = <&usb_p0_vbus>;
};
};
# Micro-USB connector with HS lines routed via controller (MUIC) and MHL
# lines connected to HDMI-MHL bridge (sii8620) on Samsung Exynos5433-based
# mobile phone
- |
muic-max77843 {
usb_con4: connector {
compatible = "samsung,usb-connector-11pin", "usb-b-connector";
label = "micro-USB";
type = "micro";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
muic_to_usb: endpoint {
remote-endpoint = <&usb_to_muic>;
};
};
port@3 {
reg = <3>;
usb_con_mhl: endpoint {
remote-endpoint = <&sii8620_mhl>;
};
};
};
};
};

18
Documentation/devicetree/bindings/crypto/fsl-dcp.txt
View File

@ -1,18 +0,0 @@
Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28 .
Required properties:
- compatible : Should be "fsl,<soc>-dcp"
- reg : Should contain MXS DCP registers location and length
- interrupts : Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
must be supplied, optionally Secure IRQ can be present, but
is currently not implemented and not used.
- clocks : Clock reference (only required on some SOCs: 6ull and 6sll).
- clock-names : Must be "dcp".
Example:
dcp: crypto@80028000 {
compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <52 53>;
};

51
Documentation/devicetree/bindings/crypto/fsl-dcp.yaml 100644
View File

@ -0,0 +1,51 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl-dcp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale DCP (Data Co-Processor) found on i.MX23/i.MX28
maintainers:
- Marek Vasut <marex@denx.de>
properties:
compatible:
enum:
- fsl,imx23-dcp
- fsl,imx28-dcp
reg:
maxItems: 1
interrupts:
description: Should contain MXS DCP interrupt numbers, VMI IRQ and DCP IRQ
must be supplied, optionally Secure IRQ can be present, but is currently
not implemented and not used.
items:
- description: MXS DCP VMI interrupt
- description: MXS DCP DCP interrupt
- description: MXS DCP secure interrupt
minItems: 2
maxItems: 3
clocks:
maxItems: 1
clock-names:
const: dcp
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
crypto@80028000 {
compatible = "fsl,imx23-dcp";
reg = <0x80028000 0x2000>;
interrupts = <53>, <54>;
};

15
Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
View File

@ -1,15 +0,0 @@
Freescale SAHARA Cryptographic Accelerator included in some i.MX chips.
Currently only i.MX27 and i.MX53 are supported.
Required properties:
- compatible : Should be "fsl,<soc>-sahara"
- reg : Should contain SAHARA registers location and length
- interrupts : Should contain SAHARA interrupt number
Example:
sah: crypto@10025000 {
compatible = "fsl,imx27-sahara";
reg = < 0x10025000 0x800>;
interrupts = <75>;
};

37
Documentation/devicetree/bindings/crypto/fsl-imx-sahara.yaml 100644
View File

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale SAHARA Cryptographic Accelerator included in some i.MX chips
maintainers:
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
properties:
compatible:
enum:
- fsl,imx27-sahara
- fsl,imx53-sahara
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
crypto@10025000 {
compatible = "fsl,imx27-sahara";
reg = < 0x10025000 0x800>;
interrupts = <75>;
};

21
Documentation/devicetree/bindings/crypto/fsl-imx-scc.txt
View File

@ -1,21 +0,0 @@
Freescale Security Controller (SCC)
Required properties:
- compatible : Should be "fsl,imx25-scc".
- reg : Should contain register location and length.
- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
- interrupt-names : Should specify the names "scm" and "smn" for the
SCM IRQ and SMN IRQ.
- clocks: Should contain the clock driving the SCC core.
- clock-names: Should be set to "ipg".
Example:
scc: crypto@53fac000 {
compatible = "fsl,imx25-scc";
reg = <0x53fac000 0x4000>;
clocks = <&clks 111>;
clock-names = "ipg";
interrupts = <49>, <50>;
interrupt-names = "scm", "smn";
};

54
Documentation/devicetree/bindings/crypto/fsl-imx-scc.yaml 100644
View File

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/fsl-imx-scc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Security Controller (SCC)
maintainers:
- Steffen Trumtrar <s.trumtrar@pengutronix.de>
properties:
compatible:
const: fsl,imx25-scc
reg:
maxItems: 1
interrupts:
items:
- description: SCC SCM interrupt
- description: SCC SMN interrupt
interrupt-names:
items:
- const: scm
- const: smn
clocks:
maxItems: 1
clock-names:
const: ipg
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
crypto@53fac000 {
compatible = "fsl,imx25-scc";
reg = <0x53fac000 0x4000>;
clocks = <&clks 111>;
clock-names = "ipg";
interrupts = <49>, <50>;
interrupt-names = "scm", "smn";
};

2
Documentation/devicetree/bindings/crypto/samsung-slimsss.yaml
View File

@ -19,7 +19,7 @@ description: |+
properties:
compatible:
items:
- const: samsung,exynos5433-slim-ss
- const: samsung,exynos5433-slim-sss
reg:
maxItems: 1

11
Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
View File

@ -11,9 +11,6 @@ maintainers:
- Maxime Ripard <mripard@kernel.org>
properties:
"#address-cells": true
"#size-cells": true
compatible:
enum:
- allwinner,sun6i-a31-mipi-dsi
@ -57,12 +54,7 @@ properties:
port should be the input endpoint, usually coming from the
associated TCON.
patternProperties:
"^panel@[0-9]+$": true
required:
- "#address-cells"
- "#size-cells"
- compatible
- reg
- interrupts
@ -74,6 +66,7 @@ required:
- port
allOf:
- $ref: dsi-controller.yaml#
- if:
properties:
compatible:
@ -99,7 +92,7 @@ allOf:
clocks:
minItems: 1
additionalProperties: false
unevaluatedProperties: false
examples:
- |

3
Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
View File

@ -9,6 +9,9 @@ title: Broadcom VC4 (VideoCore4) DSI Controller
maintainers:
- Eric Anholt <eric@anholt.net>
allOf:
- $ref: dsi-controller.yaml#
properties:
"#clock-cells":
const: 1

5
Documentation/devicetree/bindings/display/bridge/ite,it6505.yaml
View File

@ -31,6 +31,9 @@ properties:
compatible:
const: ite,it6505
reg:
maxItems: 1
ovdd-supply:
maxItems: 1
description: I/O voltage
@ -63,6 +66,8 @@ required:
- reset-gpios
- extcon
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>

3
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
View File

@ -83,6 +83,9 @@ required:
- compatible
- ports
additionalProperties: false
examples:
- |
lvds-encoder {

15
Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
View File

@ -14,6 +14,9 @@ description: |
NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
the SOCs NWL MIPI-DSI host controller.
allOf:
- $ref: ../dsi-controller.yaml#
properties:
compatible:
const: fsl,imx8mq-nwl-dsi
@ -30,6 +33,10 @@ properties:
'#size-cells':
const: 0
assigned-clock-parents: true
assigned-clock-rates: true
assigned-clocks: true
clocks:
items:
- description: DSI core clock
@ -140,10 +147,6 @@ properties:
additionalProperties: false
patternProperties:
"^panel@[0-9]+$":
type: object
required:
- '#address-cells'
- '#size-cells'
@ -159,7 +162,7 @@ required:
- reset-names
- resets
additionalProperties: false
unevaluatedProperties: false
examples:
- |
@ -168,7 +171,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/imx8mq-reset.h>
mipi_dsi: mipi_dsi@30a00000 {
dsi@30a00000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mq-nwl-dsi";

2
Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
View File

@ -66,3 +66,5 @@ required:
- clocks
- ports
- reg
additionalProperties: true

2
Documentation/devicetree/bindings/display/dsi-controller.yaml
View File

@ -73,6 +73,8 @@ patternProperties:
required:
- reg
additionalProperties: true
examples:
- |
#include <dt-bindings/gpio/gpio.h>

2
Documentation/devicetree/bindings/display/msm/gmu.yaml
View File

@ -89,6 +89,8 @@ required:
- iommus
- operating-points-v2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>

2
Documentation/devicetree/bindings/display/panel/lvds.yaml
View File

@ -112,4 +112,6 @@ oneOf:
- required:
- ports
additionalProperties: true
...

2
Documentation/devicetree/bindings/display/panel/panel-common.yaml
View File

@ -163,4 +163,6 @@ dependencies:
width-mm: [ height-mm ]
height-mm: [ width-mm ]
additionalProperties: true
...

12
Documentation/devicetree/bindings/display/panel/samsung,amoled-mipi-dsi.yaml
View File

@ -12,6 +12,17 @@ maintainers:
allOf:
- $ref: panel-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,s6e3ha2
- samsung,s6e3hf2
then:
required:
- enable-gpios
properties:
compatible:
enum:
@ -39,7 +50,6 @@ required:
- vdd3-supply
- vci-supply
- reset-gpios
- enable-gpios
additionalProperties: false

2
Documentation/devicetree/bindings/display/panel/tpo,tpg110.yaml
View File

@ -72,6 +72,8 @@ required:
- spi-max-frequency
- port
unevaluatedProperties: false
examples:
- |+
spi {

23
Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
View File

@ -13,6 +13,9 @@ maintainers:
description:
The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
allOf:
- $ref: dsi-controller.yaml#
properties:
compatible:
const: st,stm32-dsi
@ -65,24 +68,6 @@ properties:
description:
DSI output port node, connected to a panel or a bridge input port"
patternProperties:
"^(panel|panel-dsi)@[0-9]$":
type: object
description:
A node containing the panel or bridge description as documented in
Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
properties:
port:
type: object
description:
Panel or bridge port node, connected to the DSI output port (port@1)
"#address-cells":
const: 1
"#size-cells":
const: 0
required:
- "#address-cells"
- "#size-cells"
@ -92,7 +77,7 @@ required:
- clock-names
- ports
additionalProperties: false
unevaluatedProperties: false
examples:
- |

2
Documentation/devicetree/bindings/dma/dma-common.yaml
View File

@ -49,3 +49,5 @@ properties:
required:
- "#dma-cells"
additionalProperties: true

2
Documentation/devicetree/bindings/dma/dma-controller.yaml
View File

@ -17,6 +17,8 @@ properties:
$nodename:
pattern: "^dma-controller(@.*)?$"
additionalProperties: true
examples:
- |
dma: dma-controller@48000000 {

2
Documentation/devicetree/bindings/dma/dma-router.yaml
View File

@ -36,6 +36,8 @@ required:
- "#dma-cells"
- dma-masters
additionalProperties: true
examples:
- |
sdma_xbar: dma-router@4a002b78 {

2
Documentation/devicetree/bindings/dma/ingenic,dma.yaml
View File

@ -62,6 +62,8 @@ required:
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/jz4780-cgu.h>

2
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
View File

@ -81,6 +81,8 @@ required:
- clocks
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

2
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
View File

@ -33,6 +33,8 @@ required:
- reg
- dma-masters
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

2
Documentation/devicetree/bindings/dma/st,stm32-mdma.yaml
View File

@ -84,6 +84,8 @@ required:
- clocks
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>

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