hwmon: (k10temp) Add support for F15h M60h
This patch adds temperature monitoring support for F15h M60h processor. - Add new pci device id for the relevant processor - The functionality of REG_REPORTED_TEMPERATURE is moved to D0F0xBC_xD820_0CA4 [Reported Temperature Control] - So, use this to get CUR_TEMP value - Since we need an indirect register access, protect this with a mutex lock - Add Kconfig, Doc entries to indicate support for this processor. Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> Acked-by: Borislav Petkov <bp@suse.de> Acked-by: Clemens Ladisch <clemens@ladisch.de> [Guenter Roeck: Declare new mutex and function static] Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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@ -11,7 +11,7 @@ Supported chips:
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Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
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* AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
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* AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
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* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri"
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* AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri", "Carrizo"
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* AMD Family 16h processors: "Kabini", "Mullins"
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Prefix: 'k10temp'
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@ -280,8 +280,8 @@ config SENSORS_K10TEMP
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If you say yes here you get support for the temperature
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sensor(s) inside your CPU. Supported are later revisions of
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the AMD Family 10h and all revisions of the AMD Family 11h,
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12h (Llano), 14h (Brazos), 15h (Bulldozer/Trinity/Kaveri) and
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16h (Kabini/Mullins) microarchitectures.
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12h (Llano), 14h (Brazos), 15h (Bulldozer/Trinity/Kaveri/Carrizo)
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and 16h (Kabini/Mullins) microarchitectures.
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This driver can also be built as a module. If so, the module
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will be called k10temp.
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@ -33,6 +33,9 @@ static bool force;
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module_param(force, bool, 0444);
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MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
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/* Provide lock for writing to NB_SMU_IND_ADDR */
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static DEFINE_MUTEX(nb_smu_ind_mutex);
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/* CPUID function 0x80000001, ebx */
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#define CPUID_PKGTYPE_MASK 0xf0000000
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#define CPUID_PKGTYPE_F 0x00000000
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@ -51,13 +54,38 @@ MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
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#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
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#define NB_CAP_HTC 0x00000400
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/*
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* For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
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* has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
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* Control]
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*/
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#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
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#define PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 0x1573
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static void amd_nb_smu_index_read(struct pci_dev *pdev, unsigned int devfn,
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int offset, u32 *val)
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{
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mutex_lock(&nb_smu_ind_mutex);
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pci_bus_write_config_dword(pdev->bus, devfn,
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0xb8, offset);
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pci_bus_read_config_dword(pdev->bus, devfn,
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0xbc, val);
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mutex_unlock(&nb_smu_ind_mutex);
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}
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static ssize_t show_temp(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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u32 regval;
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struct pci_dev *pdev = to_pci_dev(dev);
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pci_read_config_dword(to_pci_dev(dev),
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REG_REPORTED_TEMPERATURE, ®val);
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if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == 0x60) {
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amd_nb_smu_index_read(pdev, PCI_DEVFN(0, 0),
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F15H_M60H_REPORTED_TEMP_CTRL_OFFSET,
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®val);
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} else {
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pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, ®val);
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}
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return sprintf(buf, "%u\n", (regval >> 21) * 125);
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}
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@ -211,6 +239,7 @@ static const struct pci_device_id k10temp_id_table[] = {
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
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{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
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{}
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