The main MIPS changes for a pretty light v5.3 cycle, including:
- Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes. -----BEGIN PGP SIGNATURE----- iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXS85dBUccGF1bC5idXJ0 b25AbWlwcy5jb20ACgkQPqefrLV1AN2yJwEA6SUzzTXdywxEy78Ala3tzghMjkD5 818q6a9DREGofyIA/ie08di/MIYS9++ETsaQemVXoe7KT333+SgTeXCb1lIJ =RiKE -----END PGP SIGNATURE----- Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Paul Burton: "A light batch this time around but significant improvements for certain systems: - Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes" * tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS: fix some more fall through errors in arch/mips MIPS: perf events: handle switch statement falling through warnings mips/kprobes: Export kprobe_fault_handler() MAINTAINERS: Add myself as Ingenic SoCs maintainer MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes MIPS: ralink: mt7628a.dtsi: Add pinmux DT node MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier MIPS: lantiq: Add SMP support for lantiq interrupt controller MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Move macro directly to iomem function mips: Remove q-accessors from non-64bit platforms FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h MIPS: configs: Remove useless UEVENT_HELPER_PATH ...
This commit is contained in:
commit
fa121bb3fe
27
MAINTAINERS
27
MAINTAINERS
|
@ -7955,6 +7955,33 @@ L: linux-mtd@lists.infradead.org
|
|||
S: Maintained
|
||||
F: drivers/mtd/nand/raw/ingenic/
|
||||
|
||||
INGENIC JZ47xx SoCs
|
||||
M: Paul Cercueil <paul@crapouillou.net>
|
||||
S: Maintained
|
||||
F: arch/mips/boot/dts/ingenic/
|
||||
F: arch/mips/include/asm/mach-jz4740/
|
||||
F: arch/mips/jz4740/
|
||||
F: drivers/clk/ingenic/
|
||||
F: drivers/dma/dma-jz4780.c
|
||||
F: drivers/gpu/drm/ingenic/
|
||||
F: drivers/i2c/busses/i2c-jz4780.c
|
||||
F: drivers/iio/adc/ingenic-adc.c
|
||||
F: drivers/irqchip/irq-ingenic.c
|
||||
F: drivers/memory/jz4780-nemc.c
|
||||
F: drivers/mmc/host/jz4740_mmc.c
|
||||
F: drivers/mtd/nand/raw/ingenic/
|
||||
F: drivers/pinctrl/pinctrl-ingenic.c
|
||||
F: drivers/power/supply/ingenic-battery.c
|
||||
F: drivers/pwm/pwm-jz4740.c
|
||||
F: drivers/rtc/rtc-jz4740.c
|
||||
F: drivers/tty/serial/8250/8250_ingenic.c
|
||||
F: drivers/usb/musb/jz4740.c
|
||||
F: drivers/watchdog/jz4740_wdt.c
|
||||
F: include/dt-bindings/iio/adc/ingenic,adc.h
|
||||
F: include/linux/mfd/ingenic-tcu.h
|
||||
F: sound/soc/jz4740/
|
||||
F: sound/soc/codecs/jz47*
|
||||
|
||||
INOTIFY
|
||||
M: Jan Kara <jack@suse.cz>
|
||||
R: Amir Goldstein <amir73il@gmail.com>
|
||||
|
|
|
@ -57,6 +57,7 @@ const char *get_system_type(void)
|
|||
case TITAN_CHIP_1060:
|
||||
return "TI AR7 (TNETV1060)";
|
||||
}
|
||||
/* fall through */
|
||||
default:
|
||||
return "TI AR7 (unknown)";
|
||||
}
|
||||
|
|
|
@ -153,7 +153,7 @@ static void __init ath79_detect_sys_type(void)
|
|||
case REV_ID_MAJOR_QCA9533_V2:
|
||||
ver = 2;
|
||||
ath79_soc_rev = 2;
|
||||
/* drop through */
|
||||
/* fall through */
|
||||
|
||||
case REV_ID_MAJOR_QCA9533:
|
||||
ath79_soc = ATH79_SOC_QCA9533;
|
||||
|
|
|
@ -94,6 +94,7 @@ static int __init bcm63xx_detect_flash_type(void)
|
|||
case STRAPBUS_6368_BOOT_SEL_PARALLEL:
|
||||
return BCM63XX_FLASH_TYPE_PARALLEL;
|
||||
}
|
||||
/* fall through */
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
@ -1,3 +1,5 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
@ -36,7 +38,113 @@
|
|||
|
||||
sysc: system-controller@0 {
|
||||
compatible = "ralink,mt7620a-sysc", "syscon";
|
||||
reg = <0x0 0x100>;
|
||||
reg = <0x0 0x60>;
|
||||
};
|
||||
|
||||
pinmux: pinmux@60 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x60 0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#pinctrl-cells = <2>;
|
||||
pinctrl-single,bit-per-mux;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x1>;
|
||||
|
||||
pinmux_gpio_gpio: pinmux_gpio_gpio {
|
||||
pinctrl-single,bits = <0x0 0x0 0x3>;
|
||||
};
|
||||
|
||||
pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
|
||||
pinctrl-single,bits = <0x0 0x0 0x30>;
|
||||
};
|
||||
|
||||
pinmux_i2s_gpio: pinmux_i2s_gpio {
|
||||
pinctrl-single,bits = <0x0 0x40 0xc0>;
|
||||
};
|
||||
|
||||
pinmux_uart0_uart: pinmux_uart0_uart0 {
|
||||
pinctrl-single,bits = <0x0 0x0 0x300>;
|
||||
};
|
||||
|
||||
pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc00>;
|
||||
};
|
||||
|
||||
pinmux_sdmode_gpio: pinmux_sdmode_gpio {
|
||||
pinctrl-single,bits = <0x0 0x400 0xc00>;
|
||||
};
|
||||
|
||||
pinmux_spi_spi: pinmux_spi_spi {
|
||||
pinctrl-single,bits = <0x0 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pinmux_refclk_gpio: pinmux_refclk_gpio {
|
||||
pinctrl-single,bits = <0x0 0x40000 0x40000>;
|
||||
};
|
||||
|
||||
pinmux_i2c_i2c: pinmux_i2c_i2c {
|
||||
pinctrl-single,bits = <0x0 0x0 0x300000>;
|
||||
};
|
||||
|
||||
pinmux_uart1_uart: pinmux_uart1_uart1 {
|
||||
pinctrl-single,bits = <0x0 0x0 0x3000000>;
|
||||
};
|
||||
|
||||
pinmux_uart2_uart: pinmux_uart2_uart {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm0_pwm: pinmux_pwm0_pwm {
|
||||
pinctrl-single,bits = <0x0 0x0 0x30000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm0_gpio: pinmux_pwm0_gpio {
|
||||
pinctrl-single,bits = <0x0 0x10000000
|
||||
0x30000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm1_pwm: pinmux_pwm1_pwm {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc0000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm1_gpio: pinmux_pwm1_gpio {
|
||||
pinctrl-single,bits = <0x0 0x40000000
|
||||
0xc0000000>;
|
||||
};
|
||||
|
||||
pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
|
||||
pinctrl-single,bits = <0x4 0x4 0xc>;
|
||||
};
|
||||
|
||||
pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
|
||||
pinctrl-single,bits = <0x4 0x10 0x30>;
|
||||
};
|
||||
|
||||
pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
|
||||
pinctrl-single,bits = <0x4 0x40 0xc0>;
|
||||
};
|
||||
|
||||
pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
|
||||
pinctrl-single,bits = <0x4 0x100 0x300>;
|
||||
};
|
||||
|
||||
pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
|
||||
pinctrl-single,bits = <0x4 0x400 0xc00>;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog: watchdog@100 {
|
||||
compatible = "mediatek,mt7621-wdt";
|
||||
reg = <0x100 0x30>;
|
||||
|
||||
resets = <&resetc 8>;
|
||||
reset-names = "wdt";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <24>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
intc: interrupt-controller@200 {
|
||||
|
@ -62,10 +170,42 @@
|
|||
reg = <0x300 0x100>;
|
||||
};
|
||||
|
||||
gpio: gpio@600 {
|
||||
compatible = "mediatek,mt7621-gpio";
|
||||
reg = <0x600 0x100>;
|
||||
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <6>;
|
||||
};
|
||||
|
||||
spi: spi@b00 {
|
||||
compatible = "ralink,mt7621-spi";
|
||||
reg = <0xb00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_spi_spi>;
|
||||
|
||||
resets = <&resetc 18>;
|
||||
reset-names = "spi";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uartlite@c00 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0xc00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_uart0_uart>;
|
||||
|
||||
resets = <&resetc 12>;
|
||||
reset-names = "uart0";
|
||||
|
||||
|
@ -79,6 +219,9 @@
|
|||
compatible = "ns16550a";
|
||||
reg = <0xd00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_uart1_uart>;
|
||||
|
||||
resets = <&resetc 19>;
|
||||
reset-names = "uart1";
|
||||
|
||||
|
@ -92,6 +235,9 @@
|
|||
compatible = "ns16550a";
|
||||
reg = <0xe00 0x100>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinmux_uart2_uart>;
|
||||
|
||||
resets = <&resetc 20>;
|
||||
reset-names = "uart2";
|
||||
|
||||
|
|
|
@ -485,11 +485,11 @@ cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
|
|||
config.s.qos_mask = 0xff;
|
||||
break;
|
||||
case CVMX_PKO_QUEUE_STATIC_PRIORITY:
|
||||
/* Pass 1 will fall through to the error case */
|
||||
if (!cvmx_octeon_is_pass1()) {
|
||||
config.s.qos_mask = 0xff;
|
||||
break;
|
||||
}
|
||||
/* fall through - to the error case, when Pass 1 */
|
||||
default:
|
||||
cvmx_dprintf("ERROR: cvmx_pko_config_port: Invalid "
|
||||
"priority %llu\n",
|
||||
|
|
|
@ -71,7 +71,6 @@ CONFIG_NET_ACT_POLICE=y
|
|||
CONFIG_HAMRADIO=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
|
|
|
@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y
|
|||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_DEBUGFS=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
|
||||
|
|
|
@ -37,7 +37,6 @@ CONFIG_IP_ADVANCED_ROUTER=y
|
|||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_DEBUGFS=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_REDBOOT_PARTS=y
|
||||
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-2
|
||||
|
|
|
@ -34,7 +34,6 @@ CONFIG_INET=y
|
|||
CONFIG_CFG80211=y
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_MTD=y
|
||||
|
|
|
@ -99,7 +99,6 @@ CONFIG_BPQETHER=m
|
|||
CONFIG_BAYCOM_SER_FDX=m
|
||||
CONFIG_BAYCOM_SER_HDX=m
|
||||
CONFIG_YAM=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_FW_LOADER=m
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
|
|
|
@ -26,7 +26,6 @@ CONFIG_INET=y
|
|||
CONFIG_CFG80211=y
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
|
|
|
@ -35,7 +35,6 @@ CONFIG_INET=y
|
|||
CONFIG_CFG80211=y
|
||||
CONFIG_NL80211_TESTMODE=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
|
|
|
@ -42,7 +42,6 @@ CONFIG_IP_MROUTE=y
|
|||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_MTD=y
|
||||
|
|
|
@ -44,7 +44,6 @@ CONFIG_IP_PNP_DHCP=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
|
|
|
@ -14,7 +14,6 @@ CONFIG_NET_KEY=y
|
|||
CONFIG_NET_KEY_MIGRATE=y
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_JEDECPROBE=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
|
|
|
@ -83,7 +83,6 @@ CONFIG_IP_NF_ARPFILTER=m
|
|||
CONFIG_IP_NF_ARP_MANGLE=m
|
||||
CONFIG_PHONET=m
|
||||
CONFIG_NET_9P=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_FW_LOADER=m
|
||||
CONFIG_MTD=m
|
||||
CONFIG_MTD_BLOCK=m
|
||||
|
|
|
@ -249,7 +249,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y
|
|||
CONFIG_SSB=m
|
||||
CONFIG_SSB_DRIVER_PCICORE=y
|
||||
# CONFIG_VGA_ARB is not set
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
|
|
|
@ -91,7 +91,6 @@ CONFIG_NET_ACT_SKBEDIT=m
|
|||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_CDROM_PKTCDVD=m
|
||||
|
|
|
@ -42,7 +42,6 @@ CONFIG_INET6_ESP=m
|
|||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
|
|
|
@ -77,7 +77,6 @@ CONFIG_MAC80211=m
|
|||
CONFIG_MAC80211_LEDS=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
@ -144,7 +143,6 @@ CONFIG_FB_TILEBLITTING=y
|
|||
CONFIG_FB_SIS=y
|
||||
CONFIG_FB_SIS_300=y
|
||||
CONFIG_FB_SIS_315=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GENERIC=m
|
||||
|
|
|
@ -34,7 +34,6 @@ CONFIG_SYN_COOKIES=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
|
|
|
@ -35,7 +35,6 @@ CONFIG_SYN_COOKIES=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
|
|
|
@ -97,7 +97,6 @@ CONFIG_CFG80211_WEXT=y
|
|||
CONFIG_MAC80211=m
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_RFKILL_INPUT=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_MTD=m
|
||||
|
|
|
@ -214,7 +214,6 @@ CONFIG_CFG80211=m
|
|||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_MESH=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_CONNECTOR=m
|
||||
CONFIG_MTD=y
|
||||
|
|
|
@ -219,7 +219,6 @@ CONFIG_CFG80211=m
|
|||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_MESH=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_CONNECTOR=m
|
||||
CONFIG_MTD=y
|
||||
|
|
|
@ -216,7 +216,6 @@ CONFIG_CFG80211=m
|
|||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_MESH=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_CONNECTOR=m
|
||||
CONFIG_MTD=y
|
||||
|
|
|
@ -216,7 +216,6 @@ CONFIG_CFG80211=m
|
|||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_MESH=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_CONNECTOR=m
|
||||
|
|
|
@ -39,7 +39,6 @@ CONFIG_IP_PIMSM_V1=y
|
|||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
|
|
|
@ -42,7 +42,6 @@ CONFIG_INET=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
|
|
|
@ -214,7 +214,6 @@ CONFIG_IR_IMG_RC6=y
|
|||
CONFIG_MEDIA_SUPPORT=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
# CONFIG_LCD_CLASS_DEVICE is not set
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_SOUND=y
|
||||
|
|
|
@ -25,7 +25,6 @@ CONFIG_IP_PNP=y
|
|||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_INET_AH=y
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
|
|
|
@ -41,7 +41,6 @@ CONFIG_TCP_CONG_ADVANCED=y
|
|||
CONFIG_TCP_CONG_WESTWOOD=y
|
||||
# CONFIG_TCP_CONG_HTCP is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
|
@ -77,7 +76,6 @@ CONFIG_REGULATOR=y
|
|||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_JZ4740=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
|
|
|
@ -104,7 +104,6 @@ CONFIG_NET_ACT_MIRRED=m
|
|||
CONFIG_NET_ACT_IPT=m
|
||||
CONFIG_NET_ACT_PEDIT=m
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_BLOCK2MTD=y
|
||||
|
|
|
@ -69,7 +69,6 @@ CONFIG_BRIDGE=y
|
|||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
|
|
|
@ -43,7 +43,6 @@ CONFIG_NETWORK_SECMARK=y
|
|||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_FW_LOADER=m
|
||||
CONFIG_CONNECTOR=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
|
@ -28,7 +28,6 @@ CONFIG_SYN_COOKIES=y
|
|||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
|
@ -26,7 +26,6 @@ CONFIG_SYN_COOKIES=y
|
|||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
|
@ -30,7 +30,6 @@ CONFIG_TCP_CONG_BIC=y
|
|||
CONFIG_TCP_CONG_CUBIC=m
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_BLK_DEV_LOOP=m
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
|
|
|
@ -42,7 +42,6 @@ CONFIG_INET=y
|
|||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
|
|
|
@ -71,7 +71,6 @@ CONFIG_BRIDGE=y
|
|||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
|
|
|
@ -9,6 +9,8 @@
|
|||
#ifndef _ASM_CPU_H
|
||||
#define _ASM_CPU_H
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
/*
|
||||
As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
|
||||
register 15, select 0) is defined in this (backwards compatible) way:
|
||||
|
@ -352,77 +354,70 @@ enum cpu_type_enum {
|
|||
MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
|
||||
MIPS_CPU_ISA_M64R6)
|
||||
|
||||
/*
|
||||
* Private version of BIT_ULL() to escape include file recursion hell.
|
||||
* We soon will have to switch to another mechanism that will work with
|
||||
* more than 64 bits anyway.
|
||||
*/
|
||||
#define MBIT_ULL(bit) (1ULL << (bit))
|
||||
|
||||
/*
|
||||
* CPU Option encodings
|
||||
*/
|
||||
#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
|
||||
#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
|
||||
#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
|
||||
#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
|
||||
#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
|
||||
#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
|
||||
#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
|
||||
#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
|
||||
#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
|
||||
#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
|
||||
#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
|
||||
#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
|
||||
#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
|
||||
#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
|
||||
#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
|
||||
#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
|
||||
#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
|
||||
#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
|
||||
#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
|
||||
#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
|
||||
#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
|
||||
#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
|
||||
#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
|
||||
#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
|
||||
#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
|
||||
#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
|
||||
#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
|
||||
#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
|
||||
#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
|
||||
#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
|
||||
#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
|
||||
#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
|
||||
#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
|
||||
#define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
|
||||
#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
|
||||
#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
|
||||
#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
|
||||
#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
|
||||
#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
|
||||
#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
|
||||
#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
|
||||
#define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
|
||||
#define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
|
||||
#define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
|
||||
#define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
|
||||
#define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
|
||||
#define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
|
||||
#define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
|
||||
#define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
|
||||
#define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
|
||||
#define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
|
||||
#define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
|
||||
#define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
|
||||
#define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
|
||||
#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
|
||||
#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
|
||||
#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
|
||||
#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
|
||||
#define MIPS_CPU_TX39_CACHE BIT_ULL( 4) /* TX3900-style caches */
|
||||
#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
|
||||
#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
|
||||
#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
|
||||
#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
|
||||
#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
|
||||
#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
|
||||
#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
|
||||
#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
|
||||
#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
|
||||
#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
|
||||
#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
|
||||
#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
|
||||
#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
|
||||
#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
|
||||
#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
|
||||
#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
|
||||
#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
|
||||
#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
|
||||
#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
|
||||
#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
|
||||
#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
|
||||
#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
|
||||
#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
|
||||
#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
|
||||
#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
|
||||
#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
|
||||
#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
|
||||
#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
|
||||
#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
|
||||
#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
|
||||
#define MIPS_CPU_BP_GHIST BIT_ULL(35) /* R12K+ Branch Prediction Global History */
|
||||
#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
|
||||
#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
|
||||
#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
|
||||
#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
|
||||
#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
|
||||
#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
|
||||
#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
|
||||
#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
|
||||
#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
|
||||
#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
|
||||
#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
|
||||
#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
|
||||
#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
|
||||
#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
|
||||
#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
|
||||
#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
|
||||
#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
|
||||
#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
|
||||
#define MIPS_CPU_SHARED_FTLB_RAM \
|
||||
MBIT_ULL(54) /* CPU shares FTLB RAM with another */
|
||||
BIT_ULL(54) /* CPU shares FTLB RAM with another */
|
||||
#define MIPS_CPU_SHARED_FTLB_ENTRIES \
|
||||
MBIT_ULL(55) /* CPU shares FTLB entries with another */
|
||||
BIT_ULL(55) /* CPU shares FTLB entries with another */
|
||||
#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
|
||||
MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
|
||||
#define MIPS_CPU_MMID MBIT_ULL(57) /* CPU supports MemoryMapIDs */
|
||||
BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
|
||||
#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
|
||||
|
||||
/*
|
||||
* CPU ASE encodings
|
||||
|
|
|
@ -460,7 +460,12 @@ __BUILD_MEMORY_PFX(, bwlq, type, 0)
|
|||
BUILDIO_MEM(b, u8)
|
||||
BUILDIO_MEM(w, u16)
|
||||
BUILDIO_MEM(l, u32)
|
||||
#ifdef CONFIG_64BIT
|
||||
BUILDIO_MEM(q, u64)
|
||||
#else
|
||||
__BUILD_MEMORY_PFX(__raw_, q, u64, 0)
|
||||
__BUILD_MEMORY_PFX(__mem_, q, u64, 0)
|
||||
#endif
|
||||
|
||||
#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
|
||||
__BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
|
||||
|
@ -486,12 +491,16 @@ __BUILDIO(q, u64)
|
|||
#define readb_relaxed __relaxed_readb
|
||||
#define readw_relaxed __relaxed_readw
|
||||
#define readl_relaxed __relaxed_readl
|
||||
#ifdef CONFIG_64BIT
|
||||
#define readq_relaxed __relaxed_readq
|
||||
#endif
|
||||
|
||||
#define writeb_relaxed __relaxed_writeb
|
||||
#define writew_relaxed __relaxed_writew
|
||||
#define writel_relaxed __relaxed_writel
|
||||
#ifdef CONFIG_64BIT
|
||||
#define writeq_relaxed __relaxed_writeq
|
||||
#endif
|
||||
|
||||
#define readb_be(addr) \
|
||||
__raw_readb((__force unsigned *)(addr))
|
||||
|
@ -514,8 +523,10 @@ __BUILDIO(q, u64)
|
|||
/*
|
||||
* Some code tests for these symbols
|
||||
*/
|
||||
#ifdef CONFIG_64BIT
|
||||
#define readq readq
|
||||
#define writeq writeq
|
||||
#endif
|
||||
|
||||
#define __BUILD_MEMORY_STRING(bwlq, type) \
|
||||
\
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
*
|
||||
* Copyright (C) 2012 John Crispin <john@phrozen.org>
|
||||
*/
|
||||
|
||||
|
|
|
@ -466,27 +466,27 @@ static unsigned long pin_cfg_bias_disable[] = {
|
|||
static struct pinctrl_map pin_map[] __initdata = {
|
||||
/* NAND pin configuration */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand",
|
||||
"10010000.jz4740-pinctrl", "nand", "nand-cs1"),
|
||||
"10010000.pin-controller", "nand-cs1", "nand"),
|
||||
|
||||
/* fbdev pin configuration */
|
||||
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT,
|
||||
"10010000.jz4740-pinctrl", "lcd", "lcd-8bit"),
|
||||
"10010000.pin-controller", "lcd-8bit", "lcd"),
|
||||
PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP,
|
||||
"10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"),
|
||||
"10010000.pin-controller", "lcd-no-pins", "lcd"),
|
||||
|
||||
/* MMC pin configuration */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
|
||||
"10010000.jz4740-pinctrl", "mmc", "mmc-1bit"),
|
||||
"10010000.pin-controller", "mmc-1bit", "mmc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0",
|
||||
"10010000.jz4740-pinctrl", "mmc", "mmc-4bit"),
|
||||
"10010000.pin-controller", "mmc-4bit", "mmc"),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
|
||||
"10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable),
|
||||
"10010000.pin-controller", "PD0", pin_cfg_bias_disable),
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0",
|
||||
"10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable),
|
||||
"10010000.pin-controller", "PD2", pin_cfg_bias_disable),
|
||||
|
||||
/* PWM pin configuration */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm",
|
||||
"10010000.jz4740-pinctrl", "pwm4", "pwm4"),
|
||||
"10010000.pin-controller", "pwm4", "pwm4"),
|
||||
};
|
||||
|
||||
|
||||
|
|
|
@ -333,20 +333,21 @@ void prepare_ftrace_return(unsigned long *parent_ra_addr, unsigned long self_ra,
|
|||
return;
|
||||
|
||||
/*
|
||||
* "parent_ra_addr" is the stack address saved the return address of
|
||||
* the caller of _mcount.
|
||||
* "parent_ra_addr" is the stack address where the return address of
|
||||
* the caller of _mcount is saved.
|
||||
*
|
||||
* if the gcc < 4.5, a leaf function does not save the return address
|
||||
* in the stack address, so, we "emulate" one in _mcount's stack space,
|
||||
* and hijack it directly, but for a non-leaf function, it save the
|
||||
* return address to the its own stack space, we can not hijack it
|
||||
* directly, but need to find the real stack address,
|
||||
* ftrace_get_parent_addr() does it!
|
||||
* If gcc < 4.5, a leaf function does not save the return address
|
||||
* in the stack address, so we "emulate" one in _mcount's stack space,
|
||||
* and hijack it directly.
|
||||
* For a non-leaf function, it does save the return address to its own
|
||||
* stack space, so we can not hijack it directly, but need to find the
|
||||
* real stack address, which is done by ftrace_get_parent_addr().
|
||||
*
|
||||
* if gcc>= 4.5, with the new -mmcount-ra-address option, for a
|
||||
* If gcc >= 4.5, with the new -mmcount-ra-address option, for a
|
||||
* non-leaf function, the location of the return address will be saved
|
||||
* to $12 for us, and for a leaf function, only put a zero into $12. we
|
||||
* do it in ftrace_graph_caller of mcount.S.
|
||||
* to $12 for us.
|
||||
* For a leaf function, it just puts a zero into $12, so we handle
|
||||
* it in ftrace_graph_caller() of mcount.S.
|
||||
*/
|
||||
|
||||
/* old_parent_ra = *parent_ra_addr; */
|
||||
|
|
|
@ -790,15 +790,19 @@ static void reset_counters(void *arg)
|
|||
case 4:
|
||||
mipsxx_pmu_write_control(3, 0);
|
||||
mipspmu.write_counter(3, 0);
|
||||
/* fall through */
|
||||
case 3:
|
||||
mipsxx_pmu_write_control(2, 0);
|
||||
mipspmu.write_counter(2, 0);
|
||||
/* fall through */
|
||||
case 2:
|
||||
mipsxx_pmu_write_control(1, 0);
|
||||
mipspmu.write_counter(1, 0);
|
||||
/* fall through */
|
||||
case 1:
|
||||
mipsxx_pmu_write_control(0, 0);
|
||||
mipspmu.write_counter(0, 0);
|
||||
/* fall through */
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -1380,7 +1384,7 @@ static int mipsxx_pmu_handle_shared_irq(void)
|
|||
struct perf_sample_data data;
|
||||
unsigned int counters = mipspmu.num_counters;
|
||||
u64 counter;
|
||||
int handled = IRQ_NONE;
|
||||
int n, handled = IRQ_NONE;
|
||||
struct pt_regs *regs;
|
||||
|
||||
if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
|
||||
|
@ -1401,20 +1405,16 @@ static int mipsxx_pmu_handle_shared_irq(void)
|
|||
|
||||
perf_sample_data_init(&data, 0, 0);
|
||||
|
||||
switch (counters) {
|
||||
#define HANDLE_COUNTER(n) \
|
||||
case n + 1: \
|
||||
if (test_bit(n, cpuc->used_mask)) { \
|
||||
counter = mipspmu.read_counter(n); \
|
||||
if (counter & mipspmu.overflow) { \
|
||||
handle_associated_event(cpuc, n, &data, regs); \
|
||||
handled = IRQ_HANDLED; \
|
||||
} \
|
||||
}
|
||||
HANDLE_COUNTER(3)
|
||||
HANDLE_COUNTER(2)
|
||||
HANDLE_COUNTER(1)
|
||||
HANDLE_COUNTER(0)
|
||||
for (n = counters - 1; n >= 0; n--) {
|
||||
if (!test_bit(n, cpuc->used_mask))
|
||||
continue;
|
||||
|
||||
counter = mipspmu.read_counter(n);
|
||||
if (!(counter & mipspmu.overflow))
|
||||
continue;
|
||||
|
||||
handle_associated_event(cpuc, n, &data, regs);
|
||||
handled = IRQ_HANDLED;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
|
||||
|
|
|
@ -20,13 +20,13 @@
|
|||
#include <irq.h>
|
||||
|
||||
/* register definitions - internal irqs */
|
||||
#define LTQ_ICU_IM0_ISR 0x0000
|
||||
#define LTQ_ICU_IM0_IER 0x0008
|
||||
#define LTQ_ICU_IM0_IOSR 0x0010
|
||||
#define LTQ_ICU_IM0_IRSR 0x0018
|
||||
#define LTQ_ICU_IM0_IMR 0x0020
|
||||
#define LTQ_ICU_IM1_ISR 0x0028
|
||||
#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
|
||||
#define LTQ_ICU_ISR 0x0000
|
||||
#define LTQ_ICU_IER 0x0008
|
||||
#define LTQ_ICU_IOSR 0x0010
|
||||
#define LTQ_ICU_IRSR 0x0018
|
||||
#define LTQ_ICU_IMR 0x0020
|
||||
|
||||
#define LTQ_ICU_IM_SIZE 0x28
|
||||
|
||||
/* register definitions - external irqs */
|
||||
#define LTQ_EIU_EXIN_C 0x0000
|
||||
|
@ -46,24 +46,25 @@
|
|||
*/
|
||||
#define LTQ_ICU_EBU_IRQ 22
|
||||
|
||||
#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
|
||||
#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
|
||||
#define ltq_icu_w32(vpe, m, x, y) \
|
||||
ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
|
||||
|
||||
#define ltq_icu_r32(vpe, m, x) \
|
||||
ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
|
||||
|
||||
#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
|
||||
#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
|
||||
|
||||
/* our 2 ipi interrupts for VSMP */
|
||||
#define MIPS_CPU_IPI_RESCHED_IRQ 0
|
||||
#define MIPS_CPU_IPI_CALL_IRQ 1
|
||||
|
||||
/* we have a cascade of 8 irqs */
|
||||
#define MIPS_CPU_IRQ_CASCADE 8
|
||||
|
||||
static int exin_avail;
|
||||
static u32 ltq_eiu_irq[MAX_EIU];
|
||||
static void __iomem *ltq_icu_membase[MAX_IM];
|
||||
static void __iomem *ltq_icu_membase[NR_CPUS];
|
||||
static void __iomem *ltq_eiu_membase;
|
||||
static struct irq_domain *ltq_domain;
|
||||
static DEFINE_SPINLOCK(ltq_eiu_lock);
|
||||
static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
|
||||
static int ltq_perfcount_irq;
|
||||
|
||||
int ltq_eiu_get_irq(int exin)
|
||||
|
@ -75,49 +76,84 @@ int ltq_eiu_get_irq(int exin)
|
|||
|
||||
void ltq_disable_irq(struct irq_data *d)
|
||||
{
|
||||
u32 ier = LTQ_ICU_IM0_IER;
|
||||
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
int im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
unsigned long im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long flags;
|
||||
int vpe;
|
||||
|
||||
offset %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
|
||||
|
||||
raw_spin_lock_irqsave(<q_icu_lock, flags);
|
||||
for_each_present_cpu(vpe) {
|
||||
ltq_icu_w32(vpe, im,
|
||||
ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
|
||||
LTQ_ICU_IER);
|
||||
}
|
||||
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
|
||||
}
|
||||
|
||||
void ltq_mask_and_ack_irq(struct irq_data *d)
|
||||
{
|
||||
u32 ier = LTQ_ICU_IM0_IER;
|
||||
u32 isr = LTQ_ICU_IM0_ISR;
|
||||
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
int im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
unsigned long im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long flags;
|
||||
int vpe;
|
||||
|
||||
offset %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
|
||||
ltq_icu_w32(im, BIT(offset), isr);
|
||||
|
||||
raw_spin_lock_irqsave(<q_icu_lock, flags);
|
||||
for_each_present_cpu(vpe) {
|
||||
ltq_icu_w32(vpe, im,
|
||||
ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
|
||||
LTQ_ICU_IER);
|
||||
ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
|
||||
}
|
||||
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
|
||||
}
|
||||
|
||||
static void ltq_ack_irq(struct irq_data *d)
|
||||
{
|
||||
u32 isr = LTQ_ICU_IM0_ISR;
|
||||
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
int im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
unsigned long im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long flags;
|
||||
int vpe;
|
||||
|
||||
offset %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32(im, BIT(offset), isr);
|
||||
|
||||
raw_spin_lock_irqsave(<q_icu_lock, flags);
|
||||
for_each_present_cpu(vpe) {
|
||||
ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
|
||||
}
|
||||
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
|
||||
}
|
||||
|
||||
void ltq_enable_irq(struct irq_data *d)
|
||||
{
|
||||
u32 ier = LTQ_ICU_IM0_IER;
|
||||
int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
int im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
|
||||
unsigned long im = offset / INT_NUM_IM_OFFSET;
|
||||
unsigned long flags;
|
||||
int vpe;
|
||||
|
||||
offset %= INT_NUM_IM_OFFSET;
|
||||
ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
|
||||
|
||||
vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
|
||||
|
||||
/* This shouldn't be even possible, maybe during CPU hotplug spam */
|
||||
if (unlikely(vpe >= nr_cpu_ids))
|
||||
vpe = smp_processor_id();
|
||||
|
||||
raw_spin_lock_irqsave(<q_icu_lock, flags);
|
||||
|
||||
ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
|
||||
LTQ_ICU_IER);
|
||||
|
||||
raw_spin_unlock_irqrestore(<q_icu_lock, flags);
|
||||
}
|
||||
|
||||
static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
int i;
|
||||
unsigned long flags;
|
||||
|
||||
for (i = 0; i < exin_avail; i++) {
|
||||
if (d->hwirq == ltq_eiu_irq[i]) {
|
||||
|
@ -154,8 +190,11 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
|
|||
if (edge)
|
||||
irq_set_handler(d->hwirq, handle_edge_irq);
|
||||
|
||||
ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
|
||||
(val << (i * 4)), LTQ_EIU_EXIN_C);
|
||||
spin_lock_irqsave(<q_eiu_lock, flags);
|
||||
ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
|
||||
(~(7 << (i * 4)))) | (val << (i * 4)),
|
||||
LTQ_EIU_EXIN_C);
|
||||
spin_unlock_irqrestore(<q_eiu_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -199,6 +238,21 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
|
|||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SMP)
|
||||
static int ltq_icu_irq_set_affinity(struct irq_data *d,
|
||||
const struct cpumask *cpumask, bool force)
|
||||
{
|
||||
struct cpumask tmask;
|
||||
|
||||
if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
|
||||
return -EINVAL;
|
||||
|
||||
irq_data_update_effective_affinity(d, &tmask);
|
||||
|
||||
return IRQ_SET_MASK_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct irq_chip ltq_irq_type = {
|
||||
.name = "icu",
|
||||
.irq_enable = ltq_enable_irq,
|
||||
|
@ -207,6 +261,9 @@ static struct irq_chip ltq_irq_type = {
|
|||
.irq_ack = ltq_ack_irq,
|
||||
.irq_mask = ltq_disable_irq,
|
||||
.irq_mask_ack = ltq_mask_and_ack_irq,
|
||||
#if defined(CONFIG_SMP)
|
||||
.irq_set_affinity = ltq_icu_irq_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct irq_chip ltq_eiu_type = {
|
||||
|
@ -220,15 +277,19 @@ static struct irq_chip ltq_eiu_type = {
|
|||
.irq_mask = ltq_disable_irq,
|
||||
.irq_mask_ack = ltq_mask_and_ack_irq,
|
||||
.irq_set_type = ltq_eiu_settype,
|
||||
#if defined(CONFIG_SMP)
|
||||
.irq_set_affinity = ltq_icu_irq_set_affinity,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void ltq_hw_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
int module = irq_desc_get_irq(desc) - 2;
|
||||
unsigned int module = irq_desc_get_irq(desc) - 2;
|
||||
u32 irq;
|
||||
int hwirq;
|
||||
irq_hw_number_t hwirq;
|
||||
int vpe = smp_processor_id();
|
||||
|
||||
irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
|
||||
irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
|
||||
if (irq == 0)
|
||||
return;
|
||||
|
||||
|
@ -249,6 +310,7 @@ static void ltq_hw_irq_handler(struct irq_desc *desc)
|
|||
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
||||
{
|
||||
struct irq_chip *chip = <q_irq_type;
|
||||
struct irq_data *data;
|
||||
int i;
|
||||
|
||||
if (hw < MIPS_CPU_IRQ_CASCADE)
|
||||
|
@ -258,6 +320,10 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
|
|||
if (hw == ltq_eiu_irq[i])
|
||||
chip = <q_eiu_type;
|
||||
|
||||
data = irq_get_irq_data(irq);
|
||||
|
||||
irq_data_update_effective_affinity(data, cpumask_of(0));
|
||||
|
||||
irq_set_chip_and_handler(irq, chip, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
|
@ -272,28 +338,37 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
|
|||
{
|
||||
struct device_node *eiu_node;
|
||||
struct resource res;
|
||||
int i, ret;
|
||||
int i, ret, vpe;
|
||||
|
||||
for (i = 0; i < MAX_IM; i++) {
|
||||
if (of_address_to_resource(node, i, &res))
|
||||
panic("Failed to get icu memory range");
|
||||
/* load register regions of available ICUs */
|
||||
for_each_possible_cpu(vpe) {
|
||||
if (of_address_to_resource(node, vpe, &res))
|
||||
panic("Failed to get icu%i memory range", vpe);
|
||||
|
||||
if (!request_mem_region(res.start, resource_size(&res),
|
||||
res.name))
|
||||
pr_err("Failed to request icu memory");
|
||||
pr_err("Failed to request icu%i memory\n", vpe);
|
||||
|
||||
ltq_icu_membase[i] = ioremap_nocache(res.start,
|
||||
ltq_icu_membase[vpe] = ioremap_nocache(res.start,
|
||||
resource_size(&res));
|
||||
if (!ltq_icu_membase[i])
|
||||
panic("Failed to remap icu memory");
|
||||
|
||||
if (!ltq_icu_membase[vpe])
|
||||
panic("Failed to remap icu%i memory", vpe);
|
||||
}
|
||||
|
||||
/* turn off all irqs by default */
|
||||
for (i = 0; i < MAX_IM; i++) {
|
||||
/* make sure all irqs are turned off by default */
|
||||
ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
|
||||
/* clear all possibly pending interrupts */
|
||||
ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
|
||||
for_each_possible_cpu(vpe) {
|
||||
for (i = 0; i < MAX_IM; i++) {
|
||||
/* make sure all irqs are turned off by default */
|
||||
ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
|
||||
|
||||
/* clear all possibly pending interrupts */
|
||||
ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
|
||||
ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
|
||||
|
||||
/* clear resend */
|
||||
ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
|
||||
}
|
||||
}
|
||||
|
||||
mips_cpu_irq_init();
|
||||
|
@ -347,7 +422,7 @@ unsigned int get_c0_compare_int(void)
|
|||
return CP0_LEGACY_COMPARE_IRQ;
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata of_irq_ids[] = {
|
||||
static const struct of_device_id of_irq_ids[] __initconst = {
|
||||
{ .compatible = "lantiq,icu", .data = icu_of_init },
|
||||
{},
|
||||
};
|
||||
|
|
|
@ -61,7 +61,7 @@ struct jz4780_nemc {
|
|||
*
|
||||
* Return: The number of unique NEMC banks referred to by the specified NEMC
|
||||
* child device. Unique here means that a device that references the same bank
|
||||
* multiple times in the its "reg" property will only count once.
|
||||
* multiple times in its "reg" property will only count once.
|
||||
*/
|
||||
unsigned int jz4780_nemc_num_banks(struct device *dev)
|
||||
{
|
||||
|
|
|
@ -33,6 +33,7 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/io-64-nonatomic-lo-hi.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
|
|
Loading…
Reference in a new issue