clocksource: add TI 32.768 Hz counter driver
Introduce a new clocksource driver for Texas Instruments 32.768 Hz device which is available on most OMAP-like devices. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Felipe Balbi
parent
6f82e25d2e
commit
fe851f56d5
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@ -115,6 +115,13 @@ config CLKSRC_PISTACHIO
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bool
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select CLKSRC_OF
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config CLKSRC_TI_32K
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bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST
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select CLKSRC_OF if OF
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help
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This option enables support for Texas Instruments 32.768 Hz clocksource
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available on many OMAP-like platforms.
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config CLKSRC_STM32
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bool "Clocksource for STM32 SoCs" if !ARCH_STM32
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depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
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@ -45,6 +45,7 @@ obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
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obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o
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obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
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obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o
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obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o
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obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
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obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
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126
drivers/clocksource/timer-ti-32k.c
Normal file
126
drivers/clocksource/timer-ti-32k.c
Normal file
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@ -0,0 +1,126 @@
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/**
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* timer-ti-32k.c - OMAP2 32k Timer Support
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*
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* Copyright (C) 2009 Nokia Corporation
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*
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* Update to use new clocksource/clockevent layers
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2007 MontaVista Software, Inc.
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*
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* Original driver:
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004-2009 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 of
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* the License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/sched_clock.h>
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#include <linux/clocksource.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/*
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* 32KHz clocksource ... always available, on pretty most chips except
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* OMAP 730 and 1510. Other timers could be used as clocksources, with
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* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
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* but systems won't necessarily want to spend resources that way.
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*/
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#define OMAP2_32KSYNCNT_REV_OFF 0x0
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#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
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#define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10
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#define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
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struct ti_32k {
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void __iomem *base;
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void __iomem *counter;
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struct clocksource cs;
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};
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static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
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{
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return container_of(cs, struct ti_32k, cs);
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}
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static cycle_t ti_32k_read_cycles(struct clocksource *cs)
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{
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struct ti_32k *ti = to_ti_32k(cs);
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return (cycle_t)readl_relaxed(ti->counter);
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}
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static struct ti_32k ti_32k_timer = {
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.cs = {
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.name = "32k_counter",
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.rating = 250,
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.read = ti_32k_read_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS |
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CLOCK_SOURCE_SUSPEND_NONSTOP,
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},
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};
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static u64 notrace omap_32k_read_sched_clock(void)
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{
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return ti_32k_read_cycles(&ti_32k_timer.cs);
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}
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static void __init ti_32k_timer_init(struct device_node *np)
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{
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int ret;
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ti_32k_timer.base = of_iomap(np, 0);
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if (!ti_32k_timer.base) {
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pr_err("Can't ioremap 32k timer base\n");
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return;
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}
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ti_32k_timer.counter = ti_32k_timer.base;
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/*
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* 32k sync Counter IP register offsets vary between the highlander
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* version and the legacy ones.
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*
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* The 'SCHEME' bits(30-31) of the revision register is used to identify
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* the version.
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*/
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if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
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OMAP2_32KSYNCNT_REV_SCHEME)
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
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else
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ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
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ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
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if (ret) {
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pr_err("32k_counter: can't register clocksource\n");
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return;
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}
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sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
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pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
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}
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CLOCKSOURCE_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
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ti_32k_timer_init);
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