Quanyang Wang fc076f40c8 clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable ... [ Upstream commit 394cdb69a3 ] If there is a IOCTL_SET_PLL_FRAC_MODE request sent to ATF ever, we shouldn't skip invoking PM_CLOCK_ENABLE fn even though this pll has been enabled. In ATF implementation, it will only assign the mode to the variable (struct pm_pll *)pll->mode when handling IOCTL_SET_PLL_FRAC_MODE call. Invoking PM_CLOCK_ENABLE can force ATF send request to PWU to set the pll mode to PLL's register. There is a scenario that happens in enabling VPLL_INT(clk_id:96): 1) VPLL_INT has been enabled during booting. 2) A driver calls clk_set_rate and according to the rate, the VPLL_INT should be set to FRAC mode. Then zynqmp_pll_set_mode is called to pass IOCTL_SET_PLL_FRAC_MODE to ATF. Note that at this point ATF just stores the mode to a variable. 3) This driver calls clk_prepare_enable and zynqmp_pll_enable is called to try to enable VPLL_INT pll. Because of 1), the function zynqmp_pll_enable just returns without doing anything after checking that this pll has been enabled. In the scenario above, the pll mode of VPLL_INT will never be set successfully. So adding set_pll_mode to check condition to fix it. Fixes: 3fde0e16d0 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210406153131.601701-1-quanyang.wang@windriver.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-05-14 09:50:26 +02:00
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Kconfig	…
Makefile	…
clk-gate-zynqmp.c	firmware: xilinx: Remove eemi ops for clock_getstate	2020-04-28 15:45:07 +02:00
clk-mux-zynqmp.c	firmware: xilinx: Remove eemi ops for clock set/get parent	2020-04-28 15:45:08 +02:00
clk-zynqmp.h	clk: zynqmp: Add support for custom type flags	2020-05-26 17:59:10 -07:00
clkc.c	This time around we have 4 lines of diff in the core framework, removing a	2020-06-10 11:42:19 -07:00
divider.c	This time around we have 4 lines of diff in the core framework, removing a	2020-06-10 11:42:19 -07:00
pll.c	clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enable	2021-05-14 09:50:26 +02:00