![Joakim Zhang](/assets/img/avatar_default.png)
AXI filtering is used by events 0x41 and 0x42 to count reads or writes with an ARID or AWID matching a specified filter. The filter is exposed to userspace as an (ID, MASK) pair, where each set bit in the mask causes the corresponding bit in the ID to be ignored when matching against the ID of memory transactions for the purposes of incrementing the counter. For example: # perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xff,axi_id=0x800/ cmd will count all read transactions from AXI IDs 0x800 - 0x8ff. If the 'axi_mask' is omitted, then it is treated as 0x0 which means that the 'axi_id' will be matched exactly. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Will Deacon <will@kernel.org>
626 lines
16 KiB
C
626 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2017 NXP
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* Copyright 2016 Freescale Semiconductor, Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/perf_event.h>
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#include <linux/slab.h>
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#define COUNTER_CNTL 0x0
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#define COUNTER_READ 0x20
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#define COUNTER_DPCR1 0x30
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#define CNTL_OVER 0x1
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#define CNTL_CLEAR 0x2
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#define CNTL_EN 0x4
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#define CNTL_EN_MASK 0xFFFFFFFB
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#define CNTL_CLEAR_MASK 0xFFFFFFFD
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#define CNTL_OVER_MASK 0xFFFFFFFE
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#define CNTL_CSV_SHIFT 24
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#define CNTL_CSV_MASK (0xFF << CNTL_CSV_SHIFT)
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#define EVENT_CYCLES_ID 0
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#define EVENT_CYCLES_COUNTER 0
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#define NUM_COUNTERS 4
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#define AXI_MASKING_REVERT 0xffff0000 /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
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#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu)
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#define DDR_PERF_DEV_NAME "imx8_ddr"
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#define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu"
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static DEFINE_IDA(ddr_ida);
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/* DDR Perf hardware feature */
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#define DDR_CAP_AXI_ID_FILTER 0x1 /* support AXI ID filter */
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struct fsl_ddr_devtype_data {
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unsigned int quirks; /* quirks needed for different DDR Perf core */
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};
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static const struct fsl_ddr_devtype_data imx8_devtype_data;
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static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
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.quirks = DDR_CAP_AXI_ID_FILTER,
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};
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static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
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{ .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
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{ .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
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struct ddr_pmu {
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struct pmu pmu;
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void __iomem *base;
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unsigned int cpu;
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struct hlist_node node;
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struct device *dev;
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struct perf_event *events[NUM_COUNTERS];
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int active_events;
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enum cpuhp_state cpuhp_state;
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const struct fsl_ddr_devtype_data *devtype_data;
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int irq;
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int id;
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};
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static ssize_t ddr_perf_cpumask_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct ddr_pmu *pmu = dev_get_drvdata(dev);
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return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
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}
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static struct device_attribute ddr_perf_cpumask_attr =
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__ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
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static struct attribute *ddr_perf_cpumask_attrs[] = {
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&ddr_perf_cpumask_attr.attr,
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NULL,
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};
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static struct attribute_group ddr_perf_cpumask_attr_group = {
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.attrs = ddr_perf_cpumask_attrs,
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};
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static ssize_t
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ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
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char *page)
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{
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struct perf_pmu_events_attr *pmu_attr;
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pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
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return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
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}
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#define IMX8_DDR_PMU_EVENT_ATTR(_name, _id) \
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(&((struct perf_pmu_events_attr[]) { \
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{ .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
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.id = _id, } \
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})[0].attr.attr)
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static struct attribute *ddr_perf_events_attrs[] = {
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IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
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IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
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IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
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IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
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IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
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IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
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IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
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IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
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IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
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IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
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IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
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IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
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IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
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IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
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IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
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IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
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IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
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IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
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IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
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IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
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IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
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IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
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IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
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IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
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IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
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IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
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IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
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IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
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IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
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IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
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IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
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IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
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NULL,
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};
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static struct attribute_group ddr_perf_events_attr_group = {
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.name = "events",
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.attrs = ddr_perf_events_attrs,
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};
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PMU_FORMAT_ATTR(event, "config:0-7");
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PMU_FORMAT_ATTR(axi_id, "config1:0-15");
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PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
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static struct attribute *ddr_perf_format_attrs[] = {
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&format_attr_event.attr,
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&format_attr_axi_id.attr,
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&format_attr_axi_mask.attr,
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NULL,
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};
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static struct attribute_group ddr_perf_format_attr_group = {
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.name = "format",
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.attrs = ddr_perf_format_attrs,
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};
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static const struct attribute_group *attr_groups[] = {
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&ddr_perf_events_attr_group,
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&ddr_perf_format_attr_group,
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&ddr_perf_cpumask_attr_group,
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NULL,
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};
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static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
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{
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int i;
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/*
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* Always map cycle event to counter 0
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* Cycles counter is dedicated for cycle event
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* can't used for the other events
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*/
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if (event == EVENT_CYCLES_ID) {
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if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
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return EVENT_CYCLES_COUNTER;
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else
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return -ENOENT;
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}
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for (i = 1; i < NUM_COUNTERS; i++) {
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if (pmu->events[i] == NULL)
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return i;
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}
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return -ENOENT;
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}
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static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
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{
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pmu->events[counter] = NULL;
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}
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static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
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{
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return readl_relaxed(pmu->base + COUNTER_READ + counter * 4);
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}
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static bool ddr_perf_is_filtered(struct perf_event *event)
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{
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return event->attr.config == 0x41 || event->attr.config == 0x42;
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}
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static u32 ddr_perf_filter_val(struct perf_event *event)
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{
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return event->attr.config1;
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}
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static bool ddr_perf_filters_compatible(struct perf_event *a,
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struct perf_event *b)
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{
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if (!ddr_perf_is_filtered(a))
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return true;
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if (!ddr_perf_is_filtered(b))
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return true;
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return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
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}
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static int ddr_perf_event_init(struct perf_event *event)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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struct perf_event *sibling;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
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return -EOPNOTSUPP;
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if (event->cpu < 0) {
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dev_warn(pmu->dev, "Can't provide per-task data!\n");
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return -EOPNOTSUPP;
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}
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/*
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* We must NOT create groups containing mixed PMUs, although software
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* events are acceptable (for example to create a CCN group
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* periodically read when a hrtimer aka cpu-clock leader triggers).
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*/
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if (event->group_leader->pmu != event->pmu &&
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!is_software_event(event->group_leader))
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return -EINVAL;
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if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
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if (!ddr_perf_filters_compatible(event, event->group_leader))
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return -EINVAL;
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for_each_sibling_event(sibling, event->group_leader) {
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if (!ddr_perf_filters_compatible(event, sibling))
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return -EINVAL;
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}
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}
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for_each_sibling_event(sibling, event->group_leader) {
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if (sibling->pmu != event->pmu &&
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!is_software_event(sibling))
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return -EINVAL;
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}
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event->cpu = pmu->cpu;
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hwc->idx = -1;
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return 0;
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}
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static void ddr_perf_event_update(struct perf_event *event)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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u64 delta, prev_raw_count, new_raw_count;
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int counter = hwc->idx;
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do {
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prev_raw_count = local64_read(&hwc->prev_count);
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new_raw_count = ddr_perf_read_counter(pmu, counter);
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} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
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new_raw_count) != prev_raw_count);
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delta = (new_raw_count - prev_raw_count) & 0xFFFFFFFF;
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local64_add(delta, &event->count);
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}
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static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
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int counter, bool enable)
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{
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u8 reg = counter * 4 + COUNTER_CNTL;
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int val;
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if (enable) {
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/*
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* must disable first, then enable again
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* otherwise, cycle counter will not work
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* if previous state is enabled.
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*/
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writel(0, pmu->base + reg);
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val = CNTL_EN | CNTL_CLEAR;
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val |= FIELD_PREP(CNTL_CSV_MASK, config);
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writel(val, pmu->base + reg);
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} else {
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/* Disable counter */
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writel(0, pmu->base + reg);
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}
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}
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static void ddr_perf_event_start(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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local64_set(&hwc->prev_count, 0);
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ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
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hwc->state = 0;
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}
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static int ddr_perf_event_add(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter;
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int cfg = event->attr.config;
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int cfg1 = event->attr.config1;
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if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
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int i;
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for (i = 1; i < NUM_COUNTERS; i++) {
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if (pmu->events[i] &&
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!ddr_perf_filters_compatible(event, pmu->events[i]))
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return -EINVAL;
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}
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if (ddr_perf_is_filtered(event)) {
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/* revert axi id masking(axi_mask) value */
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cfg1 ^= AXI_MASKING_REVERT;
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writel(cfg1, pmu->base + COUNTER_DPCR1);
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}
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}
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counter = ddr_perf_alloc_counter(pmu, cfg);
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if (counter < 0) {
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dev_dbg(pmu->dev, "There are not enough counters\n");
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return -EOPNOTSUPP;
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}
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pmu->events[counter] = event;
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pmu->active_events++;
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hwc->idx = counter;
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hwc->state |= PERF_HES_STOPPED;
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if (flags & PERF_EF_START)
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ddr_perf_event_start(event, flags);
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return 0;
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}
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static void ddr_perf_event_stop(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
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ddr_perf_event_update(event);
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hwc->state |= PERF_HES_STOPPED;
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}
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static void ddr_perf_event_del(struct perf_event *event, int flags)
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{
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struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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int counter = hwc->idx;
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ddr_perf_event_stop(event, PERF_EF_UPDATE);
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ddr_perf_free_counter(pmu, counter);
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pmu->active_events--;
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hwc->idx = -1;
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}
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static void ddr_perf_pmu_enable(struct pmu *pmu)
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{
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struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
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/* enable cycle counter if cycle is not active event list */
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if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
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ddr_perf_counter_enable(ddr_pmu,
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EVENT_CYCLES_ID,
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EVENT_CYCLES_COUNTER,
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true);
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}
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static void ddr_perf_pmu_disable(struct pmu *pmu)
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{
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struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
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if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
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ddr_perf_counter_enable(ddr_pmu,
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EVENT_CYCLES_ID,
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EVENT_CYCLES_COUNTER,
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false);
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}
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static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
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struct device *dev)
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{
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*pmu = (struct ddr_pmu) {
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.pmu = (struct pmu) {
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.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
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.task_ctx_nr = perf_invalid_context,
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.attr_groups = attr_groups,
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.event_init = ddr_perf_event_init,
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.add = ddr_perf_event_add,
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.del = ddr_perf_event_del,
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.start = ddr_perf_event_start,
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.stop = ddr_perf_event_stop,
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.read = ddr_perf_event_update,
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.pmu_enable = ddr_perf_pmu_enable,
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.pmu_disable = ddr_perf_pmu_disable,
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},
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.base = base,
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.dev = dev,
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};
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pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
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return pmu->id;
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}
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static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
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{
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int i;
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struct ddr_pmu *pmu = (struct ddr_pmu *) p;
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struct perf_event *event, *cycle_event = NULL;
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/* all counter will stop if cycle counter disabled */
|
|
ddr_perf_counter_enable(pmu,
|
|
EVENT_CYCLES_ID,
|
|
EVENT_CYCLES_COUNTER,
|
|
false);
|
|
/*
|
|
* When the cycle counter overflows, all counters are stopped,
|
|
* and an IRQ is raised. If any other counter overflows, it
|
|
* continues counting, and no IRQ is raised.
|
|
*
|
|
* Cycles occur at least 4 times as often as other events, so we
|
|
* can update all events on a cycle counter overflow and not
|
|
* lose events.
|
|
*
|
|
*/
|
|
for (i = 0; i < NUM_COUNTERS; i++) {
|
|
|
|
if (!pmu->events[i])
|
|
continue;
|
|
|
|
event = pmu->events[i];
|
|
|
|
ddr_perf_event_update(event);
|
|
|
|
if (event->hw.idx == EVENT_CYCLES_COUNTER)
|
|
cycle_event = event;
|
|
}
|
|
|
|
ddr_perf_counter_enable(pmu,
|
|
EVENT_CYCLES_ID,
|
|
EVENT_CYCLES_COUNTER,
|
|
true);
|
|
if (cycle_event)
|
|
ddr_perf_event_update(cycle_event);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
|
|
int target;
|
|
|
|
if (cpu != pmu->cpu)
|
|
return 0;
|
|
|
|
target = cpumask_any_but(cpu_online_mask, cpu);
|
|
if (target >= nr_cpu_ids)
|
|
return 0;
|
|
|
|
perf_pmu_migrate_context(&pmu->pmu, cpu, target);
|
|
pmu->cpu = target;
|
|
|
|
WARN_ON(irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu)));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ddr_perf_probe(struct platform_device *pdev)
|
|
{
|
|
struct ddr_pmu *pmu;
|
|
struct device_node *np;
|
|
void __iomem *base;
|
|
char *name;
|
|
int num;
|
|
int ret;
|
|
int irq;
|
|
|
|
base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(base))
|
|
return PTR_ERR(base);
|
|
|
|
np = pdev->dev.of_node;
|
|
|
|
pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
|
|
if (!pmu)
|
|
return -ENOMEM;
|
|
|
|
num = ddr_perf_init(pmu, base, &pdev->dev);
|
|
|
|
platform_set_drvdata(pdev, pmu);
|
|
|
|
name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
|
|
num);
|
|
if (!name)
|
|
return -ENOMEM;
|
|
|
|
pmu->devtype_data = of_device_get_match_data(&pdev->dev);
|
|
|
|
pmu->cpu = raw_smp_processor_id();
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
|
|
DDR_CPUHP_CB_NAME,
|
|
NULL,
|
|
ddr_perf_offline_cpu);
|
|
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
|
|
goto ddr_perf_err;
|
|
}
|
|
|
|
pmu->cpuhp_state = ret;
|
|
|
|
/* Register the pmu instance for cpu hotplug */
|
|
cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
|
|
|
|
/* Request irq */
|
|
irq = of_irq_get(np, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "Failed to get irq: %d", irq);
|
|
ret = irq;
|
|
goto ddr_perf_err;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq,
|
|
ddr_perf_irq_handler,
|
|
IRQF_NOBALANCING | IRQF_NO_THREAD,
|
|
DDR_CPUHP_CB_NAME,
|
|
pmu);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Request irq failed: %d", ret);
|
|
goto ddr_perf_err;
|
|
}
|
|
|
|
pmu->irq = irq;
|
|
ret = irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu));
|
|
if (ret) {
|
|
dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
|
|
goto ddr_perf_err;
|
|
}
|
|
|
|
ret = perf_pmu_register(&pmu->pmu, name, -1);
|
|
if (ret)
|
|
goto ddr_perf_err;
|
|
|
|
return 0;
|
|
|
|
ddr_perf_err:
|
|
if (pmu->cpuhp_state)
|
|
cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
|
|
|
|
ida_simple_remove(&ddr_ida, pmu->id);
|
|
dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
static int ddr_perf_remove(struct platform_device *pdev)
|
|
{
|
|
struct ddr_pmu *pmu = platform_get_drvdata(pdev);
|
|
|
|
cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
|
|
irq_set_affinity_hint(pmu->irq, NULL);
|
|
|
|
perf_pmu_unregister(&pmu->pmu);
|
|
|
|
ida_simple_remove(&ddr_ida, pmu->id);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx_ddr_pmu_driver = {
|
|
.driver = {
|
|
.name = "imx-ddr-pmu",
|
|
.of_match_table = imx_ddr_pmu_dt_ids,
|
|
},
|
|
.probe = ddr_perf_probe,
|
|
.remove = ddr_perf_remove,
|
|
};
|
|
|
|
module_platform_driver(imx_ddr_pmu_driver);
|
|
MODULE_LICENSE("GPL v2");
|