isci: Add firmware blob and sources
isci requires a parameter blob which is usually found in NVRAM, but it can fall back to loading with request_firmware(). These files are taken from the Linux source tree where they were wrongly added in Linux 3.0. Signed-off-by: Ben Hutchings <ben@decadent.org.uk>master
Ben Hutchings
parent
9897fdba8c
commit
de960e5045
12
WHENCE
12
WHENCE
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@ -1846,3 +1846,15 @@ File: ene-ub6250/ms_rdwr.bin
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Licence: Redistributable. See LICENCE.ene_firmware for details.
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--------------------------------------------------------------------------
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Driver: isci -- Intel C600 SAS controller driver
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File: isci/isci_firmware.bin
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Source: isci/create_fw.c
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Source: isci/create_fw.h
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Source: isci/probe_roms.h
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Source: isci/Makefile
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Licence: GPLv2
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--------------------------------------------------------------------------
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@ -0,0 +1,23 @@
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# Makefile for create_fw
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#
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CC=gcc
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CFLAGS=-c -Wall -O2 -g
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LDFLAGS=
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SOURCES=create_fw.c
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OBJECTS=$(SOURCES:.cpp=.o)
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EXECUTABLE=create_fw
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BLOB=isci_firmware.bin
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all: $(SOURCES) $(EXECUTABLE) $(BLOB)
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$(EXECUTABLE): $(OBJECTS)
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$(CC) $(LDFLAGS) $(OBJECTS) -o $@
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.c.o:
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$(CC) $(CFLAGS) $< -O $@
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$(BLOB): $(EXECUTABLE)
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./$(EXECUTABLE) >$@
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clean:
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rm -f *.o $(EXECUTABLE)
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@ -0,0 +1,36 @@
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This defines the temporary binary blow we are to pass to the SCU
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driver to emulate the binary firmware that we will eventually be
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able to access via NVRAM on the SCU controller.
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The current size of the binary blob is expected to be 149 bytes or larger
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Header Types:
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0x1: Phy Masks
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0x2: Phy Gens
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0x3: SAS Addrs
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0xff: End of Data
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ID string - u8[12]: "#SCU MAGIC#\0"
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Version - u8: 1
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SubVersion - u8: 0
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Header Type - u8: 0x1
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Size - u8: 8
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Phy Mask - u32[8]
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Header Type - u8: 0x2
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Size - u8: 8
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Phy Gen - u32[8]
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Header Type - u8: 0x3
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Size - u8: 8
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Sas Addr - u64[8]
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Header Type - u8: 0xf
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==============================================================================
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Place isci_firmware.bin in /lib/firmware
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Be sure to recreate the initramfs image to include the firmware.
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@ -0,0 +1,98 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <fcntl.h>
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#include <string.h>
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#include <errno.h>
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#include <asm/types.h>
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#include <strings.h>
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#include <stdint.h>
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#include "create_fw.h"
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int write_blob(struct isci_orom *isci_orom)
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{
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FILE *fd;
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int err;
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size_t count;
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fd = fopen(blob_name, "w+");
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if (!fd) {
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perror("Open file for write failed");
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fclose(fd);
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return -EIO;
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}
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count = fwrite(isci_orom, sizeof(struct isci_orom), 1, fd);
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if (count != 1) {
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perror("Write data failed");
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fclose(fd);
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return -EIO;
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}
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fclose(fd);
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return 0;
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}
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void set_binary_values(struct isci_orom *isci_orom)
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{
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int ctrl_idx, phy_idx, port_idx;
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/* setting OROM signature */
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strncpy(isci_orom->hdr.signature, sig, strlen(sig));
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isci_orom->hdr.version = version;
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isci_orom->hdr.total_block_length = sizeof(struct isci_orom);
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isci_orom->hdr.hdr_length = sizeof(struct sci_bios_oem_param_block_hdr);
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isci_orom->hdr.num_elements = num_elements;
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for (ctrl_idx = 0; ctrl_idx < 2; ctrl_idx++) {
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isci_orom->ctrl[ctrl_idx].controller.mode_type = mode_type;
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isci_orom->ctrl[ctrl_idx].controller.max_concurr_spin_up =
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max_num_concurrent_dev_spin_up;
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isci_orom->ctrl[ctrl_idx].controller.do_enable_ssc =
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enable_ssc;
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for (port_idx = 0; port_idx < 4; port_idx++)
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isci_orom->ctrl[ctrl_idx].ports[port_idx].phy_mask =
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phy_mask[ctrl_idx][port_idx];
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for (phy_idx = 0; phy_idx < 4; phy_idx++) {
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.high =
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(__u32)(sas_addr[ctrl_idx][phy_idx] >> 32);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].sas_address.low =
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(__u32)(sas_addr[ctrl_idx][phy_idx]);
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control0 =
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afe_tx_amp_control0;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control1 =
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afe_tx_amp_control1;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control2 =
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afe_tx_amp_control2;
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isci_orom->ctrl[ctrl_idx].phys[phy_idx].afe_tx_amp_control3 =
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afe_tx_amp_control3;
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}
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}
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}
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int main(void)
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{
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int err;
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struct isci_orom *isci_orom;
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isci_orom = malloc(sizeof(struct isci_orom));
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memset(isci_orom, 0, sizeof(struct isci_orom));
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set_binary_values(isci_orom);
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err = write_blob(isci_orom);
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if (err < 0) {
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free(isci_orom);
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return err;
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}
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free(isci_orom);
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return 0;
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}
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@ -0,0 +1,77 @@
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#ifndef _CREATE_FW_H_
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#define _CREATE_FW_H_
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#include "probe_roms.h"
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/* we are configuring for 2 SCUs */
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static const int num_elements = 2;
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/*
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* For all defined arrays:
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* elements 0-3 are for SCU0, ports 0-3
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* elements 4-7 are for SCU1, ports 0-3
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*
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* valid configurations for one SCU are:
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* P0 P1 P2 P3
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* ----------------
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* 0xF,0x0,0x0,0x0 # 1 x4 port
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* 0x3,0x0,0x4,0x8 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are each x1
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* # ports
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* 0x1,0x2,0xC,0x0 # Phys 0 and 1 are each x1 ports, phy 2 and phy 3 are a x2
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* # port
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* 0x3,0x0,0xC,0x0 # Phys 0 and 1 are a x2 port, phy 2 and phy 3 are a x2 port
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* 0x1,0x2,0x4,0x8 # Each phy is a x1 port (this is the default configuration)
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*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value assigned to UNINIT_PARAM (255).
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*/
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/* discovery mode type (port auto config mode by default ) */
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/*
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* if there is a port/phy on which you do not wish to override the default
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* values, use the value "0000000000000000". SAS address of zero's is
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* considered invalid and will not be used.
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*/
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#ifdef MPC
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static const int mode_type = SCIC_PORT_MANUAL_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4] = { {1, 2, 4, 8},
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{1, 2, 4, 8} };
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFFF0000001ULL,
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0x5FCFFFFFF0000002ULL,
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0x5FCFFFFFF0000003ULL,
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0x5FCFFFFFF0000004ULL },
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{ 0x5FCFFFFFF0000005ULL,
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0x5FCFFFFFF0000006ULL,
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0x5FCFFFFFF0000007ULL,
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0x5FCFFFFFF0000008ULL } };
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#else /* APC (default) */
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static const int mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
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static const __u8 phy_mask[2][4];
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static const unsigned long long sas_addr[2][4] = { { 0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL,
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0x5FCFFFFF00000001ULL },
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{ 0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL,
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0x5FCFFFFF00000002ULL } };
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#endif
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/* Maximum number of concurrent device spin up */
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static const int max_num_concurrent_dev_spin_up = 1;
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/* enable of ssc operation */
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static const int enable_ssc;
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/* AFE_TX_AMP_CONTROL */
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static const unsigned int afe_tx_amp_control0 = 0x000bdd08;
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static const unsigned int afe_tx_amp_control1 = 0x000ffc00;
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static const unsigned int afe_tx_amp_control2 = 0x000b7c09;
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static const unsigned int afe_tx_amp_control3 = 0x000afc6e;
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static const char blob_name[] = "isci_firmware.bin";
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static const char sig[] = "ISCUOEMB";
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static const unsigned char version = 0x10;
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#endif
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Binary file not shown.
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@ -0,0 +1,249 @@
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* BSD LICENSE
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ISCI_PROBE_ROMS_H_
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#define _ISCI_PROBE_ROMS_H_
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#ifdef __KERNEL__
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#include <linux/firmware.h>
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#include <linux/pci.h>
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#include <linux/efi.h>
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#include "isci.h"
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#define SCIC_SDS_PARM_NO_SPEED 0
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/* generation 1 (i.e. 1.5 Gb/s) */
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#define SCIC_SDS_PARM_GEN1_SPEED 1
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/* generation 2 (i.e. 3.0 Gb/s) */
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#define SCIC_SDS_PARM_GEN2_SPEED 2
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/* generation 3 (i.e. 6.0 Gb/s) */
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#define SCIC_SDS_PARM_GEN3_SPEED 3
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#define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
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/* parameters that can be set by module parameters */
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struct sci_user_parameters {
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struct sci_phy_user_params {
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/**
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* This field specifies the NOTIFY (ENABLE SPIN UP) primitive
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* insertion frequency for this phy index.
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*/
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u32 notify_enable_spin_up_insertion_frequency;
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/**
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* This method specifies the number of transmitted DWORDs within which
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* to transmit a single ALIGN primitive. This value applies regardless
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* of what type of device is attached or connection state. A value of
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* 0 indicates that no ALIGN primitives will be inserted.
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*/
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u16 align_insertion_frequency;
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/**
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* This method specifies the number of transmitted DWORDs within which
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* to transmit 2 ALIGN primitives. This applies for SAS connections
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* only. A minimum value of 3 is required for this field.
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*/
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u16 in_connection_align_insertion_frequency;
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/**
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* This field indicates the maximum speed generation to be utilized
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* by phys in the supplied port.
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* - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
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* - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
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* - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
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*/
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u8 max_speed_generation;
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} phys[SCI_MAX_PHYS];
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/**
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* This field specifies the maximum number of direct attached devices
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* that can have power supplied to them simultaneously.
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*/
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u8 max_concurr_spinup;
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/**
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* This field specifies the number of seconds to allow a phy to consume
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* power before yielding to another phy.
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*
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*/
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u8 phy_spin_up_delay_interval;
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/**
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* These timer values specifies how long a link will remain open with no
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* activity in increments of a microsecond, it can be in increments of
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* 100 microseconds if the upper most bit is set.
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*
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*/
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u16 stp_inactivity_timeout;
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u16 ssp_inactivity_timeout;
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/**
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* These timer values specifies how long a link will remain open in increments
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* of 100 microseconds.
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*
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*/
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u16 stp_max_occupancy_timeout;
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u16 ssp_max_occupancy_timeout;
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/**
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* This timer value specifies how long a link will remain open with no
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* outbound traffic in increments of a microsecond.
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*
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*/
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u8 no_outbound_task_timeout;
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};
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#define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
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#define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
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#define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
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struct sci_oem_params;
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int sci_oem_parameters_validate(struct sci_oem_params *oem);
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struct isci_orom;
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struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
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enum sci_status isci_parse_oem_parameters(struct sci_oem_params *oem,
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struct isci_orom *orom, int scu_index);
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struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
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struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
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struct isci_oem_hdr {
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u8 sig[4];
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u8 rev_major;
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u8 rev_minor;
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u16 len;
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u8 checksum;
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u8 reserved1;
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u16 reserved2;
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} __attribute__ ((packed));
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#else
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#define SCI_MAX_PORTS 4
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#define SCI_MAX_PHYS 4
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#define SCI_MAX_CONTROLLERS 2
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#endif
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#define ISCI_FW_NAME "isci/isci_firmware.bin"
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#define ROMSIGNATURE 0xaa55
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#define ISCI_OEM_SIG "$OEM"
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#define ISCI_OEM_SIG_SIZE 4
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#define ISCI_ROM_SIG "ISCUOEMB"
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#define ISCI_ROM_SIG_SIZE 8
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#define ISCI_EFI_VENDOR_GUID \
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EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
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0x1a, 0x04, 0xc6)
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#define ISCI_EFI_VAR_NAME "RstScuO"
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/* Allowed PORT configuration modes APC Automatic PORT configuration mode is
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* defined by the OEM configuration parameters providing no PHY_MASK parameters
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* for any PORT. i.e. There are no phys assigned to any of the ports at start.
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* MPC Manual PORT configuration mode is defined by the OEM configuration
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* parameters providing a PHY_MASK value for any PORT. It is assumed that any
|
||||
* PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
|
||||
* A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
|
||||
* being assigned is sufficient to declare manual PORT configuration.
|
||||
*/
|
||||
enum sci_port_configuration_mode {
|
||||
SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0,
|
||||
SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1
|
||||
};
|
||||
|
||||
struct sci_bios_oem_param_block_hdr {
|
||||
uint8_t signature[ISCI_ROM_SIG_SIZE];
|
||||
uint16_t total_block_length;
|
||||
uint8_t hdr_length;
|
||||
uint8_t version;
|
||||
uint8_t preboot_source;
|
||||
uint8_t num_elements;
|
||||
uint16_t element_length;
|
||||
uint8_t reserved[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct sci_oem_params {
|
||||
struct {
|
||||
uint8_t mode_type;
|
||||
uint8_t max_concurr_spin_up;
|
||||
uint8_t do_enable_ssc;
|
||||
uint8_t reserved;
|
||||
} controller;
|
||||
|
||||
struct {
|
||||
uint8_t phy_mask;
|
||||
} ports[SCI_MAX_PORTS];
|
||||
|
||||
struct sci_phy_oem_params {
|
||||
struct {
|
||||
uint32_t high;
|
||||
uint32_t low;
|
||||
} sas_address;
|
||||
|
||||
uint32_t afe_tx_amp_control0;
|
||||
uint32_t afe_tx_amp_control1;
|
||||
uint32_t afe_tx_amp_control2;
|
||||
uint32_t afe_tx_amp_control3;
|
||||
} phys[SCI_MAX_PHYS];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct isci_orom {
|
||||
struct sci_bios_oem_param_block_hdr hdr;
|
||||
struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue