2009-05-26 03:10:09 -06:00
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#include "../perf.h"
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#include "util.h"
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#include "parse-options.h"
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#include "parse-events.h"
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#include "exec_cmd.h"
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2009-06-01 14:50:19 -06:00
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#include "string.h"
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2009-05-26 03:10:09 -06:00
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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extern char *strcasestr(const char *haystack, const char *needle);
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2009-06-06 01:58:57 -06:00
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int nr_counters;
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2009-05-26 03:10:09 -06:00
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2009-06-06 01:58:57 -06:00
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struct perf_counter_attr attrs[MAX_COUNTERS];
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2009-05-26 03:10:09 -06:00
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struct event_symbol {
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2009-06-06 01:58:57 -06:00
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__u8 type;
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__u64 config;
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char *symbol;
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2009-05-26 03:10:09 -06:00
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};
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2009-06-06 01:58:57 -06:00
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#define C(x, y) .type = PERF_TYPE_##x, .config = PERF_COUNT_##y
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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#define CR(x, y) .type = PERF_TYPE_##x, .config = y
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2009-06-06 01:58:57 -06:00
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2009-05-26 03:10:09 -06:00
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static struct event_symbol event_symbols[] = {
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2009-06-06 01:58:57 -06:00
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{ C(HARDWARE, CPU_CYCLES), "cpu-cycles", },
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{ C(HARDWARE, CPU_CYCLES), "cycles", },
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{ C(HARDWARE, INSTRUCTIONS), "instructions", },
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{ C(HARDWARE, CACHE_REFERENCES), "cache-references", },
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{ C(HARDWARE, CACHE_MISSES), "cache-misses", },
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{ C(HARDWARE, BRANCH_INSTRUCTIONS), "branch-instructions", },
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{ C(HARDWARE, BRANCH_INSTRUCTIONS), "branches", },
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{ C(HARDWARE, BRANCH_MISSES), "branch-misses", },
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{ C(HARDWARE, BUS_CYCLES), "bus-cycles", },
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{ C(SOFTWARE, CPU_CLOCK), "cpu-clock", },
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{ C(SOFTWARE, TASK_CLOCK), "task-clock", },
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{ C(SOFTWARE, PAGE_FAULTS), "page-faults", },
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{ C(SOFTWARE, PAGE_FAULTS), "faults", },
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{ C(SOFTWARE, PAGE_FAULTS_MIN), "minor-faults", },
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{ C(SOFTWARE, PAGE_FAULTS_MAJ), "major-faults", },
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{ C(SOFTWARE, CONTEXT_SWITCHES), "context-switches", },
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{ C(SOFTWARE, CONTEXT_SWITCHES), "cs", },
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{ C(SOFTWARE, CPU_MIGRATIONS), "cpu-migrations", },
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{ C(SOFTWARE, CPU_MIGRATIONS), "migrations", },
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2009-05-26 03:10:09 -06:00
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};
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2009-05-26 01:17:18 -06:00
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#define __PERF_COUNTER_FIELD(config, name) \
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((config & PERF_COUNTER_##name##_MASK) >> PERF_COUNTER_##name##_SHIFT)
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#define PERF_COUNTER_RAW(config) __PERF_COUNTER_FIELD(config, RAW)
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#define PERF_COUNTER_CONFIG(config) __PERF_COUNTER_FIELD(config, CONFIG)
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#define PERF_COUNTER_TYPE(config) __PERF_COUNTER_FIELD(config, TYPE)
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#define PERF_COUNTER_ID(config) __PERF_COUNTER_FIELD(config, EVENT)
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static char *hw_event_names[] = {
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2009-06-06 05:58:12 -06:00
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"cycles",
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2009-05-26 01:17:18 -06:00
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"instructions",
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2009-06-06 05:58:12 -06:00
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"cache-references",
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"cache-misses",
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2009-05-26 01:17:18 -06:00
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"branches",
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2009-06-06 05:58:12 -06:00
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"branch-misses",
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"bus-cycles",
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2009-05-26 01:17:18 -06:00
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};
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static char *sw_event_names[] = {
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2009-06-06 05:58:12 -06:00
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"cpu-clock-ticks",
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"task-clock-ticks",
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"page-faults",
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"context-switches",
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"CPU-migrations",
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"minor-faults",
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"major-faults",
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2009-05-26 01:17:18 -06:00
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};
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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#define MAX_ALIASES 8
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static char *hw_cache [][MAX_ALIASES] = {
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2009-06-06 05:58:12 -06:00
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{ "L1-data" , "l1-d", "l1d", "l1" },
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{ "L1-instruction" , "l1-i", "l1i" },
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{ "L2" , "l2" },
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{ "Data-TLB" , "dtlb", "d-tlb" },
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{ "Instruction-TLB" , "itlb", "i-tlb" },
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{ "Branch" , "bpu" , "btb", "bpc" },
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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};
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static char *hw_cache_op [][MAX_ALIASES] = {
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2009-06-06 05:58:12 -06:00
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{ "Load" , "read" },
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{ "Store" , "write" },
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{ "Prefetch" , "speculative-read", "speculative-load" },
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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};
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static char *hw_cache_result [][MAX_ALIASES] = {
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2009-06-06 05:58:12 -06:00
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{ "Reference" , "ops", "access" },
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{ "Miss" },
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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};
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2009-06-06 01:58:57 -06:00
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char *event_name(int counter)
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2009-05-26 01:17:18 -06:00
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{
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2009-06-06 01:58:57 -06:00
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__u64 config = attrs[counter].config;
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int type = attrs[counter].type;
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2009-05-26 01:17:18 -06:00
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static char buf[32];
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2009-06-06 01:58:57 -06:00
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if (attrs[counter].type == PERF_TYPE_RAW) {
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sprintf(buf, "raw 0x%llx", config);
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2009-05-26 01:17:18 -06:00
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return buf;
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}
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switch (type) {
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case PERF_TYPE_HARDWARE:
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2009-06-06 01:58:57 -06:00
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if (config < PERF_HW_EVENTS_MAX)
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return hw_event_names[config];
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2009-05-26 01:17:18 -06:00
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return "unknown-hardware";
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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case PERF_TYPE_HW_CACHE: {
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__u8 cache_type, cache_op, cache_result;
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static char name[100];
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cache_type = (config >> 0) & 0xff;
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if (cache_type > PERF_COUNT_HW_CACHE_MAX)
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return "unknown-ext-hardware-cache-type";
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cache_op = (config >> 8) & 0xff;
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2009-06-06 05:58:12 -06:00
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if (cache_op > PERF_COUNT_HW_CACHE_OP_MAX)
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return "unknown-ext-hardware-cache-op";
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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cache_result = (config >> 16) & 0xff;
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2009-06-06 05:58:12 -06:00
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if (cache_result > PERF_COUNT_HW_CACHE_RESULT_MAX)
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return "unknown-ext-hardware-cache-result";
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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2009-06-06 05:58:12 -06:00
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sprintf(name, "%s-Cache-%s-%ses",
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perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
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hw_cache[cache_type][0],
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hw_cache_op[cache_op][0],
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hw_cache_result[cache_result][0]);
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return name;
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}
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|
|
2009-05-26 01:17:18 -06:00
|
|
|
case PERF_TYPE_SOFTWARE:
|
2009-06-06 01:58:57 -06:00
|
|
|
if (config < PERF_SW_EVENTS_MAX)
|
|
|
|
return sw_event_names[config];
|
2009-05-26 01:17:18 -06:00
|
|
|
return "unknown-software";
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return "unknown";
|
|
|
|
}
|
|
|
|
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
static int parse_aliases(const char *str, char *names[][MAX_ALIASES], int size)
|
|
|
|
{
|
|
|
|
int i, j;
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++) {
|
|
|
|
for (j = 0; j < MAX_ALIASES; j++) {
|
|
|
|
if (!names[i][j])
|
|
|
|
break;
|
|
|
|
if (strcasestr(str, names[i][j]))
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-06 13:04:17 -06:00
|
|
|
return -1;
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int parse_generic_hw_symbols(const char *str, struct perf_counter_attr *attr)
|
|
|
|
{
|
2009-06-06 13:04:17 -06:00
|
|
|
int cache_type = -1, cache_op = 0, cache_result = 0;
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
|
|
|
|
cache_type = parse_aliases(str, hw_cache, PERF_COUNT_HW_CACHE_MAX);
|
|
|
|
/*
|
|
|
|
* No fallback - if we cannot get a clear cache type
|
|
|
|
* then bail out:
|
|
|
|
*/
|
|
|
|
if (cache_type == -1)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
cache_op = parse_aliases(str, hw_cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
|
|
|
|
/*
|
|
|
|
* Fall back to reads:
|
|
|
|
*/
|
2009-06-06 13:04:17 -06:00
|
|
|
if (cache_op == -1)
|
|
|
|
cache_op = PERF_COUNT_HW_CACHE_OP_READ;
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
|
|
|
|
cache_result = parse_aliases(str, hw_cache_result,
|
|
|
|
PERF_COUNT_HW_CACHE_RESULT_MAX);
|
|
|
|
/*
|
|
|
|
* Fall back to accesses:
|
|
|
|
*/
|
|
|
|
if (cache_result == -1)
|
|
|
|
cache_result = PERF_COUNT_HW_CACHE_RESULT_ACCESS;
|
|
|
|
|
|
|
|
attr->config = cache_type | (cache_op << 8) | (cache_result << 16);
|
|
|
|
attr->type = PERF_TYPE_HW_CACHE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-05-26 03:10:09 -06:00
|
|
|
/*
|
|
|
|
* Each event can have multiple symbolic names.
|
|
|
|
* Symbolic names are (almost) exactly matched.
|
|
|
|
*/
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
static int parse_event_symbols(const char *str, struct perf_counter_attr *attr)
|
2009-05-26 03:10:09 -06:00
|
|
|
{
|
|
|
|
__u64 config, id;
|
|
|
|
int type;
|
|
|
|
unsigned int i;
|
2009-06-01 14:50:19 -06:00
|
|
|
const char *sep, *pstr;
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 01:58:57 -06:00
|
|
|
if (str[0] == 'r' && hex2u64(str + 1, &config) > 0) {
|
|
|
|
attr->type = PERF_TYPE_RAW;
|
|
|
|
attr->config = config;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-01 14:50:19 -06:00
|
|
|
pstr = str;
|
|
|
|
sep = strchr(pstr, ':');
|
|
|
|
if (sep) {
|
|
|
|
type = atoi(pstr);
|
|
|
|
pstr = sep + 1;
|
|
|
|
id = atoi(pstr);
|
|
|
|
sep = strchr(pstr, ':');
|
|
|
|
if (sep) {
|
|
|
|
pstr = sep + 1;
|
|
|
|
if (strchr(pstr, 'k'))
|
2009-06-06 01:58:57 -06:00
|
|
|
attr->exclude_user = 1;
|
2009-06-01 14:50:19 -06:00
|
|
|
if (strchr(pstr, 'u'))
|
2009-06-06 01:58:57 -06:00
|
|
|
attr->exclude_kernel = 1;
|
2009-06-01 14:50:19 -06:00
|
|
|
}
|
2009-06-06 01:58:57 -06:00
|
|
|
attr->type = type;
|
|
|
|
attr->config = id;
|
|
|
|
|
|
|
|
return 0;
|
2009-05-26 01:17:18 -06:00
|
|
|
}
|
2009-05-26 03:10:09 -06:00
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(event_symbols); i++) {
|
|
|
|
if (!strncmp(str, event_symbols[i].symbol,
|
2009-06-06 01:58:57 -06:00
|
|
|
strlen(event_symbols[i].symbol))) {
|
|
|
|
|
|
|
|
attr->type = event_symbols[i].type;
|
|
|
|
attr->config = event_symbols[i].config;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2009-05-26 03:10:09 -06:00
|
|
|
}
|
|
|
|
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
return parse_generic_hw_symbols(str, attr);
|
2009-05-26 03:10:09 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int parse_events(const struct option *opt, const char *str, int unset)
|
|
|
|
{
|
2009-06-06 01:58:57 -06:00
|
|
|
struct perf_counter_attr attr;
|
|
|
|
int ret;
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 01:58:57 -06:00
|
|
|
memset(&attr, 0, sizeof(attr));
|
2009-05-26 03:10:09 -06:00
|
|
|
again:
|
|
|
|
if (nr_counters == MAX_COUNTERS)
|
|
|
|
return -1;
|
|
|
|
|
perf_counter: Implement generalized cache event types
Extend generic event enumeration with the PERF_TYPE_HW_CACHE
method.
This is a 3-dimensional space:
{ L1-D, L1-I, L2, ITLB, DTLB, BPU } x
{ load, store, prefetch } x
{ accesses, misses }
User-space passes in the 3 coordinates and the kernel provides
a counter. (if the hardware supports that type and if the
combination makes sense.)
Combinations that make no sense produce a -EINVAL.
Combinations that are not supported by the hardware produce -ENOTSUP.
Extend the tools to deal with this, and rewrite the event symbol
parsing code with various popular aliases for the units and
access methods above. So 'l1-cache-miss' and 'l1d-read-ops' are
both valid aliases.
( x86 is supported for now, with the Nehalem event table filled in,
and with Core2 and Atom having placeholder tables. )
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-06-05 12:22:46 -06:00
|
|
|
ret = parse_event_symbols(str, &attr);
|
2009-06-06 01:58:57 -06:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 01:58:57 -06:00
|
|
|
attrs[nr_counters] = attr;
|
2009-05-26 03:10:09 -06:00
|
|
|
nr_counters++;
|
|
|
|
|
|
|
|
str = strstr(str, ",");
|
|
|
|
if (str) {
|
|
|
|
str++;
|
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
static const char * const event_type_descriptors[] = {
|
|
|
|
"",
|
|
|
|
"Hardware event",
|
|
|
|
"Software event",
|
|
|
|
"Tracepoint event",
|
|
|
|
"Hardware cache event",
|
|
|
|
};
|
|
|
|
|
2009-05-26 03:10:09 -06:00
|
|
|
/*
|
2009-06-06 04:24:17 -06:00
|
|
|
* Print the help text for the event symbols:
|
2009-05-26 03:10:09 -06:00
|
|
|
*/
|
2009-06-06 04:24:17 -06:00
|
|
|
void print_events(void)
|
2009-05-26 03:10:09 -06:00
|
|
|
{
|
2009-06-06 04:24:17 -06:00
|
|
|
struct event_symbol *syms = event_symbols;
|
|
|
|
unsigned int i, type, prev_type = -1;
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, "List of pre-defined events (to be used in -e):\n");
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
for (i = 0; i < ARRAY_SIZE(event_symbols); i++, syms++) {
|
|
|
|
type = syms->type + 1;
|
|
|
|
if (type > ARRAY_SIZE(event_type_descriptors))
|
|
|
|
type = 0;
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
if (type != prev_type)
|
|
|
|
fprintf(stderr, "\n");
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
fprintf(stderr, " %-30s [%s]\n", syms->symbol,
|
|
|
|
event_type_descriptors[type]);
|
2009-05-26 03:10:09 -06:00
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
prev_type = type;
|
2009-05-26 03:10:09 -06:00
|
|
|
}
|
|
|
|
|
2009-06-06 04:24:17 -06:00
|
|
|
fprintf(stderr, "\n");
|
|
|
|
fprintf(stderr, " %-30s [raw hardware event descriptor]\n",
|
|
|
|
"rNNN");
|
|
|
|
fprintf(stderr, "\n");
|
|
|
|
|
|
|
|
exit(129);
|
2009-05-26 03:10:09 -06:00
|
|
|
}
|