2009-06-18 17:48:58 -06:00
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/*
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2011-06-04 18:38:28 -06:00
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* Copyright (C) 2008, 2009 Provigent Ltd.
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2009-06-18 17:48:58 -06:00
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*
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2016-03-27 09:44:46 -06:00
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* Author: Baruch Siach <baruch@tkos.co.il>
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*
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2009-06-18 17:48:58 -06:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
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*
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* Data sheet: ARM DDI 0190B, September 2000
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*/
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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2016-03-27 09:44:46 -06:00
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#include <linux/init.h>
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2009-06-18 17:48:58 -06:00
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#include <linux/io.h>
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#include <linux/ioport.h>
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2015-11-27 10:19:15 -07:00
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#include <linux/interrupt.h>
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2009-06-18 17:48:58 -06:00
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#include <linux/irq.h>
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2013-01-18 08:31:37 -07:00
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#include <linux/irqchip/chained_irq.h>
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2009-06-18 17:48:58 -06:00
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#include <linux/bitops.h>
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#include <linux/gpio.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-02-17 04:42:51 -07:00
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#include <linux/pinctrl/consumer.h>
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2011-11-18 02:50:12 -07:00
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#include <linux/pm.h>
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2009-06-18 17:48:58 -06:00
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#define GPIODIR 0x400
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#define GPIOIS 0x404
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#define GPIOIBE 0x408
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#define GPIOIEV 0x40C
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#define GPIOIE 0x410
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#define GPIORIS 0x414
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#define GPIOMIS 0x418
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#define GPIOIC 0x41C
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#define PL061_GPIO_NR 8
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2011-11-18 02:50:12 -07:00
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#ifdef CONFIG_PM
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struct pl061_context_save_regs {
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u8 gpio_data;
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u8 gpio_dir;
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u8 gpio_is;
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u8 gpio_ibe;
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u8 gpio_iev;
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u8 gpio_ie;
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};
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#endif
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2009-06-18 17:48:58 -06:00
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2016-11-25 02:43:15 -07:00
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struct pl061 {
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2017-03-09 09:21:56 -07:00
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raw_spinlock_t lock;
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2009-06-18 17:48:58 -06:00
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void __iomem *base;
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struct gpio_chip gc;
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2016-11-25 02:41:37 -07:00
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int parent_irq;
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2011-11-18 02:50:12 -07:00
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#ifdef CONFIG_PM
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struct pl061_context_save_regs csave_regs;
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#endif
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2009-06-18 17:48:58 -06:00
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};
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2016-04-28 05:18:59 -06:00
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static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
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{
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2016-04-28 05:18:59 -06:00
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2016-11-25 02:48:40 -07:00
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return !(readb(pl061->base + GPIODIR) & BIT(offset));
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2016-04-28 05:18:59 -06:00
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}
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2009-06-18 17:48:58 -06:00
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static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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{
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2009-06-18 17:48:58 -06:00
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unsigned long flags;
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unsigned char gpiodir;
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2017-03-09 09:21:56 -07:00
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raw_spin_lock_irqsave(&pl061->lock, flags);
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2016-11-25 02:48:40 -07:00
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gpiodir = readb(pl061->base + GPIODIR);
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2014-04-26 18:00:50 -06:00
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gpiodir &= ~(BIT(offset));
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2016-11-25 02:48:40 -07:00
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writeb(gpiodir, pl061->base + GPIODIR);
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2017-03-09 09:21:56 -07:00
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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2009-06-18 17:48:58 -06:00
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return 0;
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}
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static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2009-06-18 17:48:58 -06:00
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unsigned long flags;
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unsigned char gpiodir;
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2017-03-09 09:21:56 -07:00
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raw_spin_lock_irqsave(&pl061->lock, flags);
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2016-11-25 02:48:40 -07:00
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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gpiodir = readb(pl061->base + GPIODIR);
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2014-04-26 18:00:50 -06:00
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gpiodir |= BIT(offset);
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2016-11-25 02:48:40 -07:00
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writeb(gpiodir, pl061->base + GPIODIR);
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2010-04-21 02:42:05 -06:00
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/*
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* gpio value is set again, because pl061 doesn't allow to set value of
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* a gpio pin before configuring it in OUT mode.
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*/
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2016-11-25 02:48:40 -07:00
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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2017-03-09 09:21:56 -07:00
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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2009-06-18 17:48:58 -06:00
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return 0;
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}
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static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
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{
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2009-06-18 17:48:58 -06:00
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2016-11-25 02:48:40 -07:00
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return !!readb(pl061->base + (BIT(offset + 2)));
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2009-06-18 17:48:58 -06:00
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}
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static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
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{
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2009-06-18 17:48:58 -06:00
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2016-11-25 02:48:40 -07:00
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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2009-06-18 17:48:58 -06:00
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}
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2011-01-12 18:00:16 -07:00
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static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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2009-06-18 17:48:58 -06:00
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{
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2014-03-25 03:42:35 -06:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2013-02-17 04:42:49 -07:00
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int offset = irqd_to_hwirq(d);
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2009-06-18 17:48:58 -06:00
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unsigned long flags;
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u8 gpiois, gpioibe, gpioiev;
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2013-11-26 04:59:51 -07:00
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u8 bit = BIT(offset);
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2009-06-18 17:48:58 -06:00
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2010-05-26 15:42:19 -06:00
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if (offset < 0 || offset >= PL061_GPIO_NR)
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2009-06-18 17:48:58 -06:00
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return -EINVAL;
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2015-09-17 06:21:25 -06:00
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if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
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(trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
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{
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2015-11-04 01:56:26 -07:00
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dev_err(gc->parent,
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2015-09-17 06:21:25 -06:00
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"trying to configure line %d for both level and edge "
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"detection, choose one!\n",
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offset);
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return -EINVAL;
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}
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2015-10-08 01:12:01 -06:00
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2017-03-09 09:21:56 -07:00
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raw_spin_lock_irqsave(&pl061->lock, flags);
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2015-10-08 01:12:01 -06:00
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2016-11-25 02:48:40 -07:00
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gpioiev = readb(pl061->base + GPIOIEV);
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gpiois = readb(pl061->base + GPIOIS);
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gpioibe = readb(pl061->base + GPIOIBE);
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2015-10-08 01:12:01 -06:00
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2009-06-18 17:48:58 -06:00
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if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
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2015-09-17 06:21:25 -06:00
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bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
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/* Disable edge detection */
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gpioibe &= ~bit;
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/* Enable level detection */
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2013-11-26 04:59:51 -07:00
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gpiois |= bit;
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2015-09-17 06:21:25 -06:00
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/* Select polarity */
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if (polarity)
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2013-11-26 04:59:51 -07:00
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gpioiev |= bit;
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2009-06-18 17:48:58 -06:00
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else
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2013-11-26 04:59:51 -07:00
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gpioiev &= ~bit;
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2015-09-24 18:52:52 -06:00
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irq_set_handler_locked(d, handle_level_irq);
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2015-11-04 01:56:26 -07:00
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dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
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2015-09-17 06:21:25 -06:00
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offset,
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polarity ? "HIGH" : "LOW");
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} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
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/* Disable level detection */
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gpiois &= ~bit;
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/* Select both edges, setting this makes GPIOEV be ignored */
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2013-11-26 04:59:51 -07:00
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gpioibe |= bit;
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2015-09-24 18:52:52 -06:00
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irq_set_handler_locked(d, handle_edge_irq);
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2015-11-04 01:56:26 -07:00
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dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
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2015-09-17 06:21:25 -06:00
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} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
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(trigger & IRQ_TYPE_EDGE_FALLING)) {
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bool rising = trigger & IRQ_TYPE_EDGE_RISING;
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/* Disable level detection */
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gpiois &= ~bit;
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/* Clear detection on both edges */
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2013-11-26 04:59:51 -07:00
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gpioibe &= ~bit;
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2015-09-17 06:21:25 -06:00
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/* Select edge */
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if (rising)
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2013-11-26 04:59:51 -07:00
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gpioiev |= bit;
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2015-09-17 06:21:25 -06:00
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else
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2013-11-26 04:59:51 -07:00
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gpioiev &= ~bit;
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2015-09-24 18:52:52 -06:00
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irq_set_handler_locked(d, handle_edge_irq);
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2015-11-04 01:56:26 -07:00
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dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
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2015-09-17 06:21:25 -06:00
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offset,
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rising ? "RISING" : "FALLING");
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} else {
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/* No trigger: disable everything */
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gpiois &= ~bit;
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gpioibe &= ~bit;
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gpioiev &= ~bit;
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2015-09-24 18:52:52 -06:00
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irq_set_handler_locked(d, handle_bad_irq);
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2015-11-04 01:56:26 -07:00
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dev_warn(gc->parent, "no trigger selected for line %d\n",
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2015-09-17 06:21:25 -06:00
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offset);
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2009-06-18 17:48:58 -06:00
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}
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2016-11-25 02:48:40 -07:00
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writeb(gpiois, pl061->base + GPIOIS);
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writeb(gpioibe, pl061->base + GPIOIBE);
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writeb(gpioiev, pl061->base + GPIOIEV);
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2009-06-18 17:48:58 -06:00
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2017-03-09 09:21:56 -07:00
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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2009-06-18 17:48:58 -06:00
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return 0;
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}
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2015-09-14 02:42:37 -06:00
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static void pl061_irq_handler(struct irq_desc *desc)
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2009-06-18 17:48:58 -06:00
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{
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2012-01-04 09:36:07 -07:00
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unsigned long pending;
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int offset;
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2014-03-25 03:42:35 -06:00
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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2016-11-25 02:48:40 -07:00
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struct pl061 *pl061 = gpiochip_get_data(gc);
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2011-12-09 13:12:53 -07:00
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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2009-06-18 17:48:58 -06:00
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2011-12-09 13:12:53 -07:00
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chained_irq_enter(irqchip, desc);
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2009-06-18 17:48:58 -06:00
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2016-11-25 02:48:40 -07:00
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pending = readb(pl061->base + GPIOMIS);
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2012-01-04 09:36:07 -07:00
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if (pending) {
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2010-03-05 14:41:37 -07:00
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for_each_set_bit(offset, &pending, PL061_GPIO_NR)
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2017-11-07 11:15:47 -07:00
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generic_handle_irq(irq_find_mapping(gc->irq.domain,
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2014-03-25 03:42:35 -06:00
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offset));
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2009-06-18 17:48:58 -06:00
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}
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2012-01-04 09:36:07 -07:00
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2011-12-09 13:12:53 -07:00
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chained_irq_exit(irqchip, desc);
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2009-06-18 17:48:58 -06:00
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}
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2013-02-17 04:42:49 -07:00
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static void pl061_irq_mask(struct irq_data *d)
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2011-10-21 07:05:53 -06:00
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{
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2014-03-25 03:42:35 -06:00
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|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = gpiochip_get_data(gc);
|
2014-04-26 18:00:50 -06:00
|
|
|
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
|
2013-02-17 04:42:49 -07:00
|
|
|
u8 gpioie;
|
|
|
|
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_lock(&pl061->lock);
|
2016-11-25 02:48:40 -07:00
|
|
|
gpioie = readb(pl061->base + GPIOIE) & ~mask;
|
|
|
|
writeb(gpioie, pl061->base + GPIOIE);
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_unlock(&pl061->lock);
|
2013-02-17 04:42:49 -07:00
|
|
|
}
|
2011-10-21 07:05:53 -06:00
|
|
|
|
2013-02-17 04:42:49 -07:00
|
|
|
static void pl061_irq_unmask(struct irq_data *d)
|
|
|
|
{
|
2014-03-25 03:42:35 -06:00
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = gpiochip_get_data(gc);
|
2014-04-26 18:00:50 -06:00
|
|
|
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
|
2013-02-17 04:42:49 -07:00
|
|
|
u8 gpioie;
|
|
|
|
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_lock(&pl061->lock);
|
2016-11-25 02:48:40 -07:00
|
|
|
gpioie = readb(pl061->base + GPIOIE) | mask;
|
|
|
|
writeb(gpioie, pl061->base + GPIOIE);
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_unlock(&pl061->lock);
|
2013-02-17 04:42:49 -07:00
|
|
|
}
|
|
|
|
|
2015-09-24 18:52:52 -06:00
|
|
|
/**
|
|
|
|
* pl061_irq_ack() - ACK an edge IRQ
|
|
|
|
* @d: IRQ data for this IRQ
|
|
|
|
*
|
|
|
|
* This gets called from the edge IRQ handler to ACK the edge IRQ
|
|
|
|
* in the GPIOIC (interrupt-clear) register. For level IRQs this is
|
|
|
|
* not needed: these go away when the level signal goes away.
|
|
|
|
*/
|
|
|
|
static void pl061_irq_ack(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = gpiochip_get_data(gc);
|
2015-09-24 18:52:52 -06:00
|
|
|
u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
|
|
|
|
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_lock(&pl061->lock);
|
2016-11-25 02:48:40 -07:00
|
|
|
writeb(mask, pl061->base + GPIOIC);
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_unlock(&pl061->lock);
|
2015-09-24 18:52:52 -06:00
|
|
|
}
|
|
|
|
|
2015-11-27 10:19:15 -07:00
|
|
|
static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
|
|
|
|
{
|
|
|
|
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = gpiochip_get_data(gc);
|
2015-11-27 10:19:15 -07:00
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
return irq_set_irq_wake(pl061->parent_irq, state);
|
2015-11-27 10:19:15 -07:00
|
|
|
}
|
|
|
|
|
2013-02-17 04:42:49 -07:00
|
|
|
static struct irq_chip pl061_irqchip = {
|
2013-11-26 06:19:44 -07:00
|
|
|
.name = "pl061",
|
2015-09-24 18:52:52 -06:00
|
|
|
.irq_ack = pl061_irq_ack,
|
2013-02-17 04:42:49 -07:00
|
|
|
.irq_mask = pl061_irq_mask,
|
|
|
|
.irq_unmask = pl061_irq_unmask,
|
|
|
|
.irq_set_type = pl061_irq_type,
|
2015-11-27 10:19:15 -07:00
|
|
|
.irq_set_wake = pl061_irq_set_wake,
|
2013-02-17 04:42:49 -07:00
|
|
|
};
|
|
|
|
|
2012-10-05 03:45:28 -06:00
|
|
|
static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
|
2009-06-18 17:48:58 -06:00
|
|
|
{
|
2012-10-05 03:45:28 -06:00
|
|
|
struct device *dev = &adev->dev;
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061;
|
2016-11-25 03:02:19 -07:00
|
|
|
int ret, irq;
|
2009-06-18 17:48:58 -06:00
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
|
|
|
|
if (pl061 == NULL)
|
2009-06-18 17:48:58 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061->base = devm_ioremap_resource(dev, &adev->res);
|
|
|
|
if (IS_ERR(pl061->base))
|
|
|
|
return PTR_ERR(pl061->base);
|
2009-06-18 17:48:58 -06:00
|
|
|
|
2017-03-09 09:21:56 -07:00
|
|
|
raw_spin_lock_init(&pl061->lock);
|
2015-10-11 09:34:18 -06:00
|
|
|
if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061->gc.request = gpiochip_generic_request;
|
|
|
|
pl061->gc.free = gpiochip_generic_free;
|
2015-10-11 09:34:18 -06:00
|
|
|
}
|
2009-06-18 17:48:58 -06:00
|
|
|
|
2016-11-25 03:02:19 -07:00
|
|
|
pl061->gc.base = -1;
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061->gc.get_direction = pl061_get_direction;
|
|
|
|
pl061->gc.direction_input = pl061_direction_input;
|
|
|
|
pl061->gc.direction_output = pl061_direction_output;
|
|
|
|
pl061->gc.get = pl061_get_value;
|
|
|
|
pl061->gc.set = pl061_set_value;
|
|
|
|
pl061->gc.ngpio = PL061_GPIO_NR;
|
|
|
|
pl061->gc.label = dev_name(dev);
|
|
|
|
pl061->gc.parent = dev;
|
|
|
|
pl061->gc.owner = THIS_MODULE;
|
|
|
|
|
|
|
|
ret = gpiochip_add_data(&pl061->gc, pl061);
|
2009-06-18 17:48:58 -06:00
|
|
|
if (ret)
|
2012-10-05 03:45:28 -06:00
|
|
|
return ret;
|
2009-06-18 17:48:58 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* irq_chip support
|
|
|
|
*/
|
2016-11-25 02:48:40 -07:00
|
|
|
writeb(0, pl061->base + GPIOIE); /* disable irqs */
|
2012-10-05 03:45:28 -06:00
|
|
|
irq = adev->irq[0];
|
2013-11-22 02:11:49 -07:00
|
|
|
if (irq < 0) {
|
|
|
|
dev_err(&adev->dev, "invalid IRQ\n");
|
2012-10-05 03:45:28 -06:00
|
|
|
return -ENODEV;
|
2013-11-22 02:11:49 -07:00
|
|
|
}
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061->parent_irq = irq;
|
2012-10-05 03:45:28 -06:00
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
ret = gpiochip_irqchip_add(&pl061->gc, &pl061_irqchip,
|
2016-11-25 03:02:19 -07:00
|
|
|
0, handle_bad_irq,
|
2014-03-25 03:42:35 -06:00
|
|
|
IRQ_TYPE_NONE);
|
|
|
|
if (ret) {
|
|
|
|
dev_info(&adev->dev, "could not add irqchip\n");
|
|
|
|
return ret;
|
2013-11-22 02:11:49 -07:00
|
|
|
}
|
2016-11-25 02:48:40 -07:00
|
|
|
gpiochip_set_chained_irqchip(&pl061->gc, &pl061_irqchip,
|
2014-03-25 03:42:35 -06:00
|
|
|
irq, pl061_irq_handler);
|
2013-11-27 00:47:02 -07:00
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
amba_set_drvdata(adev, pl061);
|
2014-02-26 04:12:37 -07:00
|
|
|
dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
|
|
|
|
&adev->res.start);
|
2011-11-18 02:50:12 -07:00
|
|
|
|
2009-06-18 17:48:58 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-18 02:50:12 -07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int pl061_suspend(struct device *dev)
|
|
|
|
{
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = dev_get_drvdata(dev);
|
2011-11-18 02:50:12 -07:00
|
|
|
int offset;
|
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061->csave_regs.gpio_data = 0;
|
|
|
|
pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
|
|
|
|
pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
|
|
|
|
pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
|
|
|
|
pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
|
|
|
|
pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
|
2011-11-18 02:50:12 -07:00
|
|
|
|
|
|
|
for (offset = 0; offset < PL061_GPIO_NR; offset++) {
|
2016-11-25 02:48:40 -07:00
|
|
|
if (pl061->csave_regs.gpio_dir & (BIT(offset)))
|
|
|
|
pl061->csave_regs.gpio_data |=
|
|
|
|
pl061_get_value(&pl061->gc, offset) << offset;
|
2011-11-18 02:50:12 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pl061_resume(struct device *dev)
|
|
|
|
{
|
2016-11-25 02:48:40 -07:00
|
|
|
struct pl061 *pl061 = dev_get_drvdata(dev);
|
2011-11-18 02:50:12 -07:00
|
|
|
int offset;
|
|
|
|
|
|
|
|
for (offset = 0; offset < PL061_GPIO_NR; offset++) {
|
2016-11-25 02:48:40 -07:00
|
|
|
if (pl061->csave_regs.gpio_dir & (BIT(offset)))
|
|
|
|
pl061_direction_output(&pl061->gc, offset,
|
|
|
|
pl061->csave_regs.gpio_data &
|
2014-04-26 18:00:50 -06:00
|
|
|
(BIT(offset)));
|
2011-11-18 02:50:12 -07:00
|
|
|
else
|
2016-11-25 02:48:40 -07:00
|
|
|
pl061_direction_input(&pl061->gc, offset);
|
2011-11-18 02:50:12 -07:00
|
|
|
}
|
|
|
|
|
2016-11-25 02:48:40 -07:00
|
|
|
writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
|
|
|
|
writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
|
|
|
|
writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
|
|
|
|
writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
|
2011-11-18 02:50:12 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-01-11 02:55:20 -07:00
|
|
|
static const struct dev_pm_ops pl061_dev_pm_ops = {
|
|
|
|
.suspend = pl061_suspend,
|
|
|
|
.resume = pl061_resume,
|
|
|
|
.freeze = pl061_suspend,
|
|
|
|
.restore = pl061_resume,
|
|
|
|
};
|
2011-11-18 02:50:12 -07:00
|
|
|
#endif
|
|
|
|
|
2017-08-23 10:15:09 -06:00
|
|
|
static const struct amba_id pl061_ids[] = {
|
2009-06-18 17:48:58 -06:00
|
|
|
{
|
|
|
|
.id = 0x00041061,
|
|
|
|
.mask = 0x000fffff,
|
|
|
|
},
|
|
|
|
{ 0, 0 },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct amba_driver pl061_gpio_driver = {
|
|
|
|
.drv = {
|
|
|
|
.name = "pl061_gpio",
|
2011-11-18 02:50:12 -07:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
.pm = &pl061_dev_pm_ops,
|
|
|
|
#endif
|
2009-06-18 17:48:58 -06:00
|
|
|
},
|
|
|
|
.id_table = pl061_ids,
|
|
|
|
.probe = pl061_probe,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init pl061_gpio_init(void)
|
|
|
|
{
|
|
|
|
return amba_driver_register(&pl061_gpio_driver);
|
|
|
|
}
|
2016-03-27 09:44:46 -06:00
|
|
|
device_initcall(pl061_gpio_init);
|