2007-01-26 00:28:18 -07:00
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/*
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* Support for IDE interfaces on Celleb platform
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*
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* (C) Copyright 2006 TOSHIBA CORPORATION
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*
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* This code is based on drivers/ata/ata_piix.c:
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* Copyright 2003-2005 Red Hat Inc
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* Copyright 2003-2005 Jeff Garzik
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* Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
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* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
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2008-10-27 09:09:10 -06:00
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* Copyright (C) 2003 Red Hat Inc
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2007-01-26 00:28:18 -07:00
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*
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* and drivers/ata/ahci.c:
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* Copyright 2004-2005 Red Hat, Inc.
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*
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* and drivers/ata/libata-core.c:
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* Copyright 2003-2004 Red Hat, Inc. All rights reserved.
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* Copyright 2003-2004 Jeff Garzik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#define DRV_NAME "pata_scc"
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2007-08-31 02:54:06 -06:00
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#define DRV_VERSION "0.3"
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2007-01-26 00:28:18 -07:00
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#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
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/* PCI BARs */
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#define SCC_CTRL_BAR 0
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#define SCC_BMID_BAR 1
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/* offset of CTRL registers */
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#define SCC_CTL_PIOSHT 0x000
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#define SCC_CTL_PIOCT 0x004
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#define SCC_CTL_MDMACT 0x008
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#define SCC_CTL_MCRCST 0x00C
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#define SCC_CTL_SDMACT 0x010
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#define SCC_CTL_SCRCST 0x014
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#define SCC_CTL_UDENVT 0x018
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#define SCC_CTL_TDVHSEL 0x020
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#define SCC_CTL_MODEREG 0x024
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#define SCC_CTL_ECMODE 0xF00
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#define SCC_CTL_MAEA0 0xF50
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#define SCC_CTL_MAEC0 0xF54
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#define SCC_CTL_CCKCTRL 0xFF0
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/* offset of BMID registers */
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#define SCC_DMA_CMD 0x000
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#define SCC_DMA_STATUS 0x004
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#define SCC_DMA_TABLE_OFS 0x008
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#define SCC_DMA_INTMASK 0x010
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#define SCC_DMA_INTST 0x014
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#define SCC_DMA_PTERADD 0x018
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#define SCC_REG_CMD_ADDR 0x020
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#define SCC_REG_DATA 0x000
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#define SCC_REG_ERR 0x004
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#define SCC_REG_FEATURE 0x004
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#define SCC_REG_NSECT 0x008
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#define SCC_REG_LBAL 0x00C
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#define SCC_REG_LBAM 0x010
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#define SCC_REG_LBAH 0x014
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#define SCC_REG_DEVICE 0x018
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#define SCC_REG_STATUS 0x01C
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#define SCC_REG_CMD 0x01C
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#define SCC_REG_ALTSTATUS 0x020
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/* register value */
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#define TDVHSEL_MASTER 0x00000001
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#define TDVHSEL_SLAVE 0x00000004
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#define MODE_JCUSFEN 0x00000080
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#define ECMODE_VALUE 0x01
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#define CCKCTRL_ATARESET 0x00040000
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#define CCKCTRL_BUFCNT 0x00020000
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#define CCKCTRL_CRST 0x00010000
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#define CCKCTRL_OCLKEN 0x00000100
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#define CCKCTRL_ATACLKOEN 0x00000002
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#define CCKCTRL_LCLKEN 0x00000001
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#define QCHCD_IOS_SS 0x00000001
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#define QCHSD_STPDIAG 0x00020000
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#define INTMASK_MSK 0xD1000012
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#define INTSTS_SERROR 0x80000000
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#define INTSTS_PRERR 0x40000000
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#define INTSTS_RERR 0x10000000
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#define INTSTS_ICERR 0x01000000
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#define INTSTS_BMSINT 0x00000010
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#define INTSTS_BMHE 0x00000008
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#define INTSTS_IOIRQS 0x00000004
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#define INTSTS_INTRQ 0x00000002
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#define INTSTS_ACTEINT 0x00000001
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/* PIO transfer mode table */
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/* JCHST */
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static const unsigned long JCHSTtbl[2][7] = {
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{0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
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{0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
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};
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/* JCHHT */
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static const unsigned long JCHHTtbl[2][7] = {
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{0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
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{0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
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};
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/* JCHCT */
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static const unsigned long JCHCTtbl[2][7] = {
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{0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
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{0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
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};
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/* DMA transfer mode table */
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/* JCHDCTM/JCHDCTS */
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static const unsigned long JCHDCTxtbl[2][7] = {
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{0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
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{0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
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};
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/* JCSTWTM/JCSTWTS */
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static const unsigned long JCSTWTxtbl[2][7] = {
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{0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
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{0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
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};
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/* JCTSS */
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static const unsigned long JCTSStbl[2][7] = {
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{0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
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{0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
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};
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/* JCENVT */
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static const unsigned long JCENVTtbl[2][7] = {
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{0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
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{0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
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};
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/* JCACTSELS/JCACTSELM */
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static const unsigned long JCACTSELtbl[2][7] = {
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{0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
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{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
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};
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static const struct pci_device_id scc_pci_tbl[] = {
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2010-07-15 12:39:43 -06:00
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{ PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
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2007-01-26 00:28:18 -07:00
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{ } /* terminate list */
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};
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/**
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* scc_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: um
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*
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* Set PIO mode for device.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
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void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
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void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
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void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
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unsigned long reg;
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int offset;
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reg = in_be32(cckctrl_port);
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if (reg & CCKCTRL_ATACLKOEN)
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offset = 1; /* 133MHz */
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else
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offset = 0; /* 100MHz */
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reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
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out_be32(piosht_port, reg);
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reg = JCHCTtbl[offset][pio];
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out_be32(pioct_port, reg);
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}
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/**
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* scc_set_dmamode - Initialize host controller PATA DMA timings
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* @ap: Port whose timings we are configuring
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* @adev: um
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*
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* Set UDMA mode for device.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int udma = adev->dma_mode;
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unsigned int is_slave = (adev->devno != 0);
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u8 speed = udma;
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void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
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void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
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void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
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void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
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void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
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void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
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void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
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void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
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int offset, idx;
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2007-02-26 03:51:33 -07:00
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if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
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2007-01-26 00:28:18 -07:00
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offset = 1; /* 133MHz */
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else
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offset = 0; /* 100MHz */
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if (speed >= XFER_UDMA_0)
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idx = speed - XFER_UDMA_0;
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else
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return;
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if (is_slave) {
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out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
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out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
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out_be32(tdvhsel_port,
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(in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
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} else {
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out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
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out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
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out_be32(tdvhsel_port,
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(in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
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}
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out_be32(udenvt_port,
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JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
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}
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2007-07-16 21:10:17 -06:00
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unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
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{
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/* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
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if (adev->class == ATA_DEV_ATAPI &&
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(mask & (0xE0 << ATA_SHIFT_UDMA))) {
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printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
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mask &= ~(0xE0 << ATA_SHIFT_UDMA);
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}
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libata-sff: clean up BMDMA initialization
When BMDMA initialization failed or BMDMA was not available for
whatever reason, bmdma_addr was left at zero and used as an indication
that BMDMA shouldn't be used. This leads to the following problems.
p1. For BMDMA drivers which don't use traditional BMDMA register,
ata_bmdma_mode_filter() incorrectly inhibits DMA modes. Those
drivers either have to inherit from ata_sff_port_ops or clear
->mode_filter explicitly.
p2. non-BMDMA drivers call into BMDMA PRD table allocation. It
doesn't actually allocate PRD table if bmdma_addr is not
initialized but is still confusing.
p3. For BMDMA drivers which don't use traditional BMDMA register, some
methods might not be invoked as expected (e.g. bmdma_stop from
ata_sff_post_internal_cmd()).
p4. SFF drivers w/ custom DMA interface implement noop BMDMA ops
worrying libata core might call into one of them.
These problems are caused by the muddy line between SFF and BMDMA and
the assumption that all BMDMA controllers initialize bmdma_addr.
This patch fixes p1 and p2 by removing the bmdma_addr assumption and
moving prd allocation to BMDMA port start. Later patches will fix the
remaining issues.
This patch improves BMDMA initialization such that
* When BMDMA register initialization fails, falls back to PIO instead
of failing. ata_pci_bmdma_init() never fails now.
* When ata_pci_bmdma_init() falls back to PIO, it clears
ap->mwdma_mask and udma_mask instead of depending on
ata_bmdma_mode_filter(). This makes ata_bmdma_mode_filter()
unnecessary thus resolving p1.
* ata_port_start() which actually is BMDMA specific is moved to
ata_bmdma_port_start(). ata_port_start() and ata_sff_port_start()
are killed.
* ata_sff_port_start32() is moved and renamed to
ata_bmdma_port_start32().
Drivers which no longer call into PRD table allocation are...
pdc_adma, sata_inic162x, sata_qstor, sata_sx4, pata_cmd640 and all
drivers which inherit from ata_sff_port_ops.
pata_icside sets ->port_start to ATA_OP_NULL as it doesn't need PRD
but is a BMDMA controller and doesn't have custom port_start like
other such controllers.
Note that with the previous patch which makes all and only BMDMA
drivers inherit from ata_bmdma_port_ops, this change doesn't break
drivers which need PRD table.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-05-10 13:41:34 -06:00
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return mask;
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2007-07-16 21:10:17 -06:00
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}
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2007-01-26 00:28:18 -07:00
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/**
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* scc_tf_load - send taskfile registers to host controller
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* @ap: Port to which output is sent
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* @tf: ATA taskfile register set
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*
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2008-04-07 07:47:16 -06:00
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* Note: Original code is ata_sff_tf_load().
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2007-01-26 00:28:18 -07:00
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*/
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static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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out_be32(ioaddr->ctl_addr, tf->ctl);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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out_be32(ioaddr->feature_addr, tf->hob_feature);
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out_be32(ioaddr->nsect_addr, tf->hob_nsect);
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|
|
out_be32(ioaddr->lbal_addr, tf->hob_lbal);
|
|
|
|
out_be32(ioaddr->lbam_addr, tf->hob_lbam);
|
|
|
|
out_be32(ioaddr->lbah_addr, tf->hob_lbah);
|
|
|
|
VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
|
|
|
|
tf->hob_feature,
|
|
|
|
tf->hob_nsect,
|
|
|
|
tf->hob_lbal,
|
|
|
|
tf->hob_lbam,
|
|
|
|
tf->hob_lbah);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (is_addr) {
|
|
|
|
out_be32(ioaddr->feature_addr, tf->feature);
|
|
|
|
out_be32(ioaddr->nsect_addr, tf->nsect);
|
|
|
|
out_be32(ioaddr->lbal_addr, tf->lbal);
|
|
|
|
out_be32(ioaddr->lbam_addr, tf->lbam);
|
|
|
|
out_be32(ioaddr->lbah_addr, tf->lbah);
|
|
|
|
VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
|
|
|
|
tf->feature,
|
|
|
|
tf->nsect,
|
|
|
|
tf->lbal,
|
|
|
|
tf->lbam,
|
|
|
|
tf->lbah);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tf->flags & ATA_TFLAG_DEVICE) {
|
|
|
|
out_be32(ioaddr->device_addr, tf->device);
|
|
|
|
VPRINTK("device 0x%X\n", tf->device);
|
|
|
|
}
|
|
|
|
|
|
|
|
ata_wait_idle(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_check_status - Read device status reg & clear interrupt
|
|
|
|
* @ap: port where the device is
|
|
|
|
*
|
|
|
|
* Note: Original code is ata_check_status().
|
|
|
|
*/
|
|
|
|
|
|
|
|
static u8 scc_check_status (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
return in_be32(ap->ioaddr.status_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_tf_read - input device's ATA taskfile shadow registers
|
|
|
|
* @ap: Port from which input is read
|
|
|
|
* @tf: ATA taskfile register set for storing input
|
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_tf_read().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
|
|
|
|
{
|
|
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
|
|
|
|
tf->command = scc_check_status(ap);
|
|
|
|
tf->feature = in_be32(ioaddr->error_addr);
|
|
|
|
tf->nsect = in_be32(ioaddr->nsect_addr);
|
|
|
|
tf->lbal = in_be32(ioaddr->lbal_addr);
|
|
|
|
tf->lbam = in_be32(ioaddr->lbam_addr);
|
|
|
|
tf->lbah = in_be32(ioaddr->lbah_addr);
|
|
|
|
tf->device = in_be32(ioaddr->device_addr);
|
|
|
|
|
|
|
|
if (tf->flags & ATA_TFLAG_LBA48) {
|
|
|
|
out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
|
|
|
|
tf->hob_feature = in_be32(ioaddr->error_addr);
|
|
|
|
tf->hob_nsect = in_be32(ioaddr->nsect_addr);
|
|
|
|
tf->hob_lbal = in_be32(ioaddr->lbal_addr);
|
|
|
|
tf->hob_lbam = in_be32(ioaddr->lbam_addr);
|
|
|
|
tf->hob_lbah = in_be32(ioaddr->lbah_addr);
|
2007-07-20 05:44:44 -06:00
|
|
|
out_be32(ioaddr->ctl_addr, tf->ctl);
|
|
|
|
ap->last_ctl = tf->ctl;
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_exec_command - issue ATA command to host controller
|
|
|
|
* @ap: port to which command is being issued
|
|
|
|
* @tf: ATA taskfile register set
|
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_exec_command().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_exec_command (struct ata_port *ap,
|
|
|
|
const struct ata_taskfile *tf)
|
|
|
|
{
|
2007-02-21 00:36:33 -07:00
|
|
|
DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
out_be32(ap->ioaddr.command_addr, tf->command);
|
2008-04-07 07:47:16 -06:00
|
|
|
ata_sff_pause(ap);
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_check_altstatus - Read device alternate status reg
|
|
|
|
* @ap: port where the device is
|
|
|
|
*/
|
|
|
|
|
|
|
|
static u8 scc_check_altstatus (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
return in_be32(ap->ioaddr.altstatus_addr);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-04-07 07:47:16 -06:00
|
|
|
* scc_dev_select - Select device 0/1 on ATA bus
|
2007-01-26 00:28:18 -07:00
|
|
|
* @ap: ATA channel to manipulate
|
|
|
|
* @device: ATA device (numbered from zero) to select
|
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_dev_select().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
static void scc_dev_select (struct ata_port *ap, unsigned int device)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
|
|
|
u8 tmp;
|
|
|
|
|
|
|
|
if (device == 0)
|
|
|
|
tmp = ATA_DEVICE_OBS;
|
|
|
|
else
|
|
|
|
tmp = ATA_DEVICE_OBS | ATA_DEV1;
|
|
|
|
|
|
|
|
out_be32(ap->ioaddr.device_addr, tmp);
|
2008-04-07 07:47:16 -06:00
|
|
|
ata_sff_pause(ap);
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
2010-05-07 12:47:50 -06:00
|
|
|
/**
|
|
|
|
* scc_set_devctl - Write device control reg
|
|
|
|
* @ap: port where the device is
|
|
|
|
* @ctl: value to write
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_set_devctl(struct ata_port *ap, u8 ctl)
|
|
|
|
{
|
|
|
|
out_be32(ap->ioaddr.ctl_addr, ctl);
|
|
|
|
}
|
|
|
|
|
2007-01-26 00:28:18 -07:00
|
|
|
/**
|
|
|
|
* scc_bmdma_setup - Set up PCI IDE BMDMA transaction
|
|
|
|
* @qc: Info associated with this ATA transaction.
|
|
|
|
*
|
|
|
|
* Note: Original code is ata_bmdma_setup().
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_bmdma_setup (struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
|
|
|
|
u8 dmactl;
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
|
|
|
|
|
|
|
/* load PRD table addr */
|
2010-05-10 13:41:41 -06:00
|
|
|
out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* specify data direction, triple-check start bit is clear */
|
|
|
|
dmactl = in_be32(mmio + SCC_DMA_CMD);
|
|
|
|
dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
|
|
|
|
if (!rw)
|
|
|
|
dmactl |= ATA_DMA_WR;
|
|
|
|
out_be32(mmio + SCC_DMA_CMD, dmactl);
|
|
|
|
|
|
|
|
/* issue r/w command */
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_exec_command(ap, &qc->tf);
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_bmdma_start - Start a PCI IDE BMDMA transaction
|
|
|
|
* @qc: Info associated with this ATA transaction.
|
|
|
|
*
|
|
|
|
* Note: Original code is ata_bmdma_start().
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_bmdma_start (struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
u8 dmactl;
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
|
|
|
|
|
|
|
/* start host DMA transaction */
|
|
|
|
dmactl = in_be32(mmio + SCC_DMA_CMD);
|
|
|
|
out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_devchk - PATA device presence detection
|
|
|
|
* @ap: ATA channel to examine
|
|
|
|
* @device: Device to examine (starting at zero)
|
|
|
|
*
|
|
|
|
* Note: Original code is ata_devchk().
|
|
|
|
*/
|
|
|
|
|
|
|
|
static unsigned int scc_devchk (struct ata_port *ap,
|
|
|
|
unsigned int device)
|
|
|
|
{
|
|
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
u8 nsect, lbal;
|
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, device);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
out_be32(ioaddr->nsect_addr, 0x55);
|
|
|
|
out_be32(ioaddr->lbal_addr, 0xaa);
|
|
|
|
|
|
|
|
out_be32(ioaddr->nsect_addr, 0xaa);
|
|
|
|
out_be32(ioaddr->lbal_addr, 0x55);
|
|
|
|
|
|
|
|
out_be32(ioaddr->nsect_addr, 0x55);
|
|
|
|
out_be32(ioaddr->lbal_addr, 0xaa);
|
|
|
|
|
|
|
|
nsect = in_be32(ioaddr->nsect_addr);
|
|
|
|
lbal = in_be32(ioaddr->lbal_addr);
|
|
|
|
|
|
|
|
if ((nsect == 0x55) && (lbal == 0xaa))
|
|
|
|
return 1; /* we found a device */
|
|
|
|
|
|
|
|
return 0; /* nothing found */
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-04-07 07:47:19 -06:00
|
|
|
* scc_wait_after_reset - wait for devices to become ready after reset
|
2007-01-26 00:28:18 -07:00
|
|
|
*
|
2008-04-07 07:47:19 -06:00
|
|
|
* Note: Original code is ata_sff_wait_after_reset
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2010-04-24 10:29:45 -06:00
|
|
|
static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
|
|
|
|
unsigned long deadline)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
2008-04-07 07:47:19 -06:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-01-26 00:28:18 -07:00
|
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
unsigned int dev0 = devmask & (1 << 0);
|
|
|
|
unsigned int dev1 = devmask & (1 << 1);
|
2008-04-07 07:47:19 -06:00
|
|
|
int rc, ret = 0;
|
|
|
|
|
|
|
|
/* Spec mandates ">= 2ms" before checking status. We wait
|
|
|
|
* 150ms, because that was the magic delay used for ATAPI
|
|
|
|
* devices in Hale Landis's ATADRVR, for the period of time
|
|
|
|
* between when the ATA command register is written, and then
|
|
|
|
* status is checked. Because waiting for "a while" before
|
|
|
|
* checking status is fine, post SRST, we perform this magic
|
|
|
|
* delay here as well.
|
|
|
|
*
|
|
|
|
* Old drivers/ide uses the 2mS rule and then waits for ready.
|
|
|
|
*/
|
2010-09-06 09:56:29 -06:00
|
|
|
ata_msleep(ap, 150);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2008-04-07 07:47:19 -06:00
|
|
|
/* always check readiness of the master device */
|
|
|
|
rc = ata_sff_wait_ready(link, deadline);
|
|
|
|
/* -ENODEV means the odd clown forgot the D7 pulldown resistor
|
|
|
|
* and TF status is 0xff, bail out on it too.
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
2008-04-07 07:47:19 -06:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2008-04-07 07:47:19 -06:00
|
|
|
/* if device 1 was found in ata_devchk, wait for register
|
|
|
|
* access briefly, then wait for BSY to clear.
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
2008-04-07 07:47:19 -06:00
|
|
|
if (dev1) {
|
|
|
|
int i;
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 1);
|
2008-04-07 07:47:19 -06:00
|
|
|
|
|
|
|
/* Wait for register access. Some ATAPI devices fail
|
|
|
|
* to set nsect/lbal after reset, so don't waste too
|
|
|
|
* much time on it. We're gonna wait for !BSY anyway.
|
|
|
|
*/
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
u8 nsect, lbal;
|
|
|
|
|
|
|
|
nsect = in_be32(ioaddr->nsect_addr);
|
|
|
|
lbal = in_be32(ioaddr->lbal_addr);
|
|
|
|
if ((nsect == 1) && (lbal == 1))
|
|
|
|
break;
|
2010-09-06 09:56:29 -06:00
|
|
|
ata_msleep(ap, 50); /* give drive a breather */
|
2008-04-07 07:47:19 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
rc = ata_sff_wait_ready(link, deadline);
|
|
|
|
if (rc) {
|
|
|
|
if (rc != -ENODEV)
|
|
|
|
return rc;
|
|
|
|
ret = rc;
|
|
|
|
}
|
2007-05-23 15:26:43 -06:00
|
|
|
}
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* is all this really necessary? */
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 0);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (dev1)
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 1);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (dev0)
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 0);
|
2007-05-23 15:26:43 -06:00
|
|
|
|
2008-04-07 07:47:19 -06:00
|
|
|
return ret;
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_bus_softreset - PATA device software reset
|
|
|
|
*
|
|
|
|
* Note: Original code is ata_bus_softreset().
|
|
|
|
*/
|
|
|
|
|
2014-08-17 08:30:09 -06:00
|
|
|
static int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
|
2007-05-23 15:26:43 -06:00
|
|
|
unsigned long deadline)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
|
|
|
struct ata_ioports *ioaddr = &ap->ioaddr;
|
|
|
|
|
2007-02-21 00:36:33 -07:00
|
|
|
DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* software reset. causes dev0 to be selected */
|
|
|
|
out_be32(ioaddr->ctl_addr, ap->ctl);
|
|
|
|
udelay(20);
|
|
|
|
out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
|
|
|
|
udelay(20);
|
|
|
|
out_be32(ioaddr->ctl_addr, ap->ctl);
|
|
|
|
|
2014-08-17 08:30:09 -06:00
|
|
|
return scc_wait_after_reset(&ap->link, devmask, deadline);
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-04-07 07:47:16 -06:00
|
|
|
* scc_softreset - reset host port via ATA SRST
|
2007-01-26 00:28:18 -07:00
|
|
|
* @ap: port to reset
|
|
|
|
* @classes: resulting classes of attached devices
|
2007-05-23 15:26:43 -06:00
|
|
|
* @deadline: deadline jiffies for the operation
|
2007-01-26 00:28:18 -07:00
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_softreset().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
static int scc_softreset(struct ata_link *link, unsigned int *classes,
|
|
|
|
unsigned long deadline)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
2007-09-21 20:50:09 -06:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-01-26 00:28:18 -07:00
|
|
|
unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
|
2014-08-17 08:30:09 -06:00
|
|
|
unsigned int devmask = 0;
|
|
|
|
int rc;
|
2007-01-26 00:28:18 -07:00
|
|
|
u8 err;
|
|
|
|
|
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
/* determine if device 0/1 are present */
|
|
|
|
if (scc_devchk(ap, 0))
|
|
|
|
devmask |= (1 << 0);
|
|
|
|
if (slave_possible && scc_devchk(ap, 1))
|
|
|
|
devmask |= (1 << 1);
|
|
|
|
|
|
|
|
/* select device 0 again */
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 0);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* issue bus reset */
|
|
|
|
DPRINTK("about to softreset, devmask=%x\n", devmask);
|
2014-08-17 08:30:09 -06:00
|
|
|
rc = scc_bus_softreset(ap, devmask, deadline);
|
|
|
|
if (rc) {
|
|
|
|
ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", rc);
|
2007-01-26 00:28:18 -07:00
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* determine by signature whether we have ATA or ATAPI devices */
|
2008-04-07 07:47:16 -06:00
|
|
|
classes[0] = ata_sff_dev_classify(&ap->link.device[0],
|
2007-09-02 08:23:57 -06:00
|
|
|
devmask & (1 << 0), &err);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (slave_possible && err != 0x81)
|
2008-04-07 07:47:16 -06:00
|
|
|
classes[1] = ata_sff_dev_classify(&ap->link.device[1],
|
2007-09-02 08:23:57 -06:00
|
|
|
devmask & (1 << 1), &err);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_bmdma_stop - Stop PCI IDE BMDMA transfer
|
|
|
|
* @qc: Command we are ending DMA for
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_bmdma_stop (struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
|
|
|
void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
|
|
|
|
void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
|
|
|
|
u32 reg;
|
|
|
|
|
|
|
|
while (1) {
|
|
|
|
reg = in_be32(bmid_base + SCC_DMA_INTST);
|
|
|
|
|
|
|
|
if (reg & INTSTS_SERROR) {
|
|
|
|
printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
|
|
|
|
out_be32(bmid_base + SCC_DMA_CMD,
|
|
|
|
in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_PRERR) {
|
|
|
|
u32 maea0, maec0;
|
|
|
|
maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
|
|
|
|
maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
|
|
|
|
printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
|
|
|
|
out_be32(bmid_base + SCC_DMA_CMD,
|
|
|
|
in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_RERR) {
|
|
|
|
printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
|
|
|
|
out_be32(bmid_base + SCC_DMA_CMD,
|
|
|
|
in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_ICERR) {
|
|
|
|
out_be32(bmid_base + SCC_DMA_CMD,
|
|
|
|
in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
|
|
|
|
printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_BMSINT) {
|
|
|
|
unsigned int classes;
|
2008-05-19 11:17:51 -06:00
|
|
|
unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
|
2007-01-26 00:28:18 -07:00
|
|
|
printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
|
|
|
|
/* TBD: SW reset */
|
2008-04-07 07:47:16 -06:00
|
|
|
scc_softreset(&ap->link, &classes, deadline);
|
2007-01-26 00:28:18 -07:00
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_BMHE) {
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_ACTEINT) {
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reg & INTSTS_IOIRQS) {
|
|
|
|
out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* clear start/stop bit */
|
|
|
|
out_be32(bmid_base + SCC_DMA_CMD,
|
|
|
|
in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
|
|
|
|
|
|
|
|
/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
|
2008-05-29 15:10:58 -06:00
|
|
|
ata_sff_dma_pause(ap); /* dummy read */
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_bmdma_status - Read PCI IDE BMDMA status
|
|
|
|
* @ap: Port associated with this ATA transaction.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static u8 scc_bmdma_status (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
2007-07-10 03:29:34 -06:00
|
|
|
u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
|
|
|
|
u32 int_status = in_be32(mmio + SCC_DMA_INTST);
|
2007-09-21 20:50:09 -06:00
|
|
|
struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
2007-07-10 03:29:34 -06:00
|
|
|
static int retry = 0;
|
|
|
|
|
|
|
|
/* return if IOS_SS is cleared */
|
|
|
|
if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
|
|
|
|
return host_stat;
|
|
|
|
|
|
|
|
/* errata A252,A308 workaround: Step4 */
|
2008-05-29 15:10:58 -06:00
|
|
|
if ((scc_check_altstatus(ap) & ATA_ERR)
|
|
|
|
&& (int_status & INTSTS_INTRQ))
|
2007-07-10 03:29:34 -06:00
|
|
|
return (host_stat | ATA_DMA_INTR);
|
|
|
|
|
|
|
|
/* errata A308 workaround Step5 */
|
|
|
|
if (int_status & INTSTS_IOIRQS) {
|
|
|
|
host_stat |= ATA_DMA_INTR;
|
|
|
|
|
|
|
|
/* We don't check ATAPI DMA because it is limited to UDMA4 */
|
|
|
|
if ((qc->tf.protocol == ATA_PROT_DMA &&
|
|
|
|
qc->dev->xfer_mode > XFER_UDMA_4)) {
|
|
|
|
if (!(int_status & INTSTS_ACTEINT)) {
|
2007-07-16 21:10:17 -06:00
|
|
|
printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
|
|
|
|
ap->print_id);
|
2007-07-10 03:29:34 -06:00
|
|
|
host_stat |= ATA_DMA_ERR;
|
|
|
|
if (retry++)
|
2007-07-16 21:10:17 -06:00
|
|
|
ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
|
2007-07-10 03:29:34 -06:00
|
|
|
} else
|
|
|
|
retry = 0;
|
|
|
|
}
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
return host_stat;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_data_xfer - Transfer data by PIO
|
2007-12-05 00:43:07 -07:00
|
|
|
* @dev: device for this I/O
|
2007-01-26 00:28:18 -07:00
|
|
|
* @buf: data buffer
|
|
|
|
* @buflen: buffer length
|
2007-12-05 00:43:07 -07:00
|
|
|
* @rw: read/write
|
2007-01-26 00:28:18 -07:00
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_data_xfer().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2007-12-05 00:43:07 -07:00
|
|
|
static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
|
|
|
|
unsigned int buflen, int rw)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
2007-12-05 00:43:07 -07:00
|
|
|
struct ata_port *ap = dev->link->ap;
|
2007-01-26 00:28:18 -07:00
|
|
|
unsigned int words = buflen >> 1;
|
|
|
|
unsigned int i;
|
2008-03-24 23:18:11 -06:00
|
|
|
__le16 *buf16 = (__le16 *) buf;
|
2007-01-26 00:28:18 -07:00
|
|
|
void __iomem *mmio = ap->ioaddr.data_addr;
|
|
|
|
|
|
|
|
/* Transfer multiple of 2 bytes */
|
2007-12-05 00:43:07 -07:00
|
|
|
if (rw == READ)
|
2007-01-26 00:28:18 -07:00
|
|
|
for (i = 0; i < words; i++)
|
2008-03-24 23:18:11 -06:00
|
|
|
buf16[i] = cpu_to_le16(in_be32(mmio));
|
2007-12-05 00:43:07 -07:00
|
|
|
else
|
|
|
|
for (i = 0; i < words; i++)
|
2008-03-24 23:18:11 -06:00
|
|
|
out_be32(mmio, le16_to_cpu(buf16[i]));
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* Transfer trailing 1 byte, if any. */
|
|
|
|
if (unlikely(buflen & 0x01)) {
|
2008-03-24 23:18:11 -06:00
|
|
|
__le16 align_buf[1] = { 0 };
|
2007-01-26 00:28:18 -07:00
|
|
|
unsigned char *trailing_buf = buf + buflen - 1;
|
|
|
|
|
2007-12-05 00:43:07 -07:00
|
|
|
if (rw == READ) {
|
2008-03-24 23:18:11 -06:00
|
|
|
align_buf[0] = cpu_to_le16(in_be32(mmio));
|
2007-01-26 00:28:18 -07:00
|
|
|
memcpy(trailing_buf, align_buf, 1);
|
2007-12-05 00:43:07 -07:00
|
|
|
} else {
|
|
|
|
memcpy(align_buf, trailing_buf, 1);
|
2008-03-24 23:18:11 -06:00
|
|
|
out_be32(mmio, le16_to_cpu(align_buf[0]));
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
2007-12-05 00:43:07 -07:00
|
|
|
words++;
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
2007-12-05 00:43:07 -07:00
|
|
|
|
|
|
|
return words << 1;
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-04-07 07:47:16 -06:00
|
|
|
* scc_postreset - standard postreset callback
|
2007-01-26 00:28:18 -07:00
|
|
|
* @ap: the target ata_port
|
|
|
|
* @classes: classes of attached devices
|
|
|
|
*
|
2008-04-07 07:47:16 -06:00
|
|
|
* Note: Original code is ata_sff_postreset().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
static void scc_postreset(struct ata_link *link, unsigned int *classes)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
2007-09-21 20:50:09 -06:00
|
|
|
struct ata_port *ap = link->ap;
|
|
|
|
|
2007-01-26 00:28:18 -07:00
|
|
|
DPRINTK("ENTER\n");
|
|
|
|
|
|
|
|
/* is double-select really necessary? */
|
|
|
|
if (classes[0] != ATA_DEV_NONE)
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 1);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (classes[1] != ATA_DEV_NONE)
|
2008-04-07 07:47:16 -06:00
|
|
|
ap->ops->sff_dev_select(ap, 0);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
/* bail out if no device is present */
|
|
|
|
if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
|
|
|
|
DPRINTK("EXIT, no device\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set up device control */
|
2010-04-24 10:29:58 -06:00
|
|
|
out_be32(ap->ioaddr.ctl_addr, ap->ctl);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
DPRINTK("EXIT\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2008-04-07 07:47:16 -06:00
|
|
|
* scc_irq_clear - Clear PCI IDE BMDMA interrupt.
|
2007-01-26 00:28:18 -07:00
|
|
|
* @ap: Port associated with this ATA transaction.
|
|
|
|
*
|
2010-05-19 14:10:20 -06:00
|
|
|
* Note: Original code is ata_bmdma_irq_clear().
|
2007-01-26 00:28:18 -07:00
|
|
|
*/
|
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
static void scc_irq_clear (struct ata_port *ap)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
|
|
|
|
|
|
|
if (!mmio)
|
|
|
|
return;
|
|
|
|
|
|
|
|
out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_port_start - Set port up for dma.
|
|
|
|
* @ap: Port to initialize
|
|
|
|
*
|
libata-sff: clean up BMDMA initialization
When BMDMA initialization failed or BMDMA was not available for
whatever reason, bmdma_addr was left at zero and used as an indication
that BMDMA shouldn't be used. This leads to the following problems.
p1. For BMDMA drivers which don't use traditional BMDMA register,
ata_bmdma_mode_filter() incorrectly inhibits DMA modes. Those
drivers either have to inherit from ata_sff_port_ops or clear
->mode_filter explicitly.
p2. non-BMDMA drivers call into BMDMA PRD table allocation. It
doesn't actually allocate PRD table if bmdma_addr is not
initialized but is still confusing.
p3. For BMDMA drivers which don't use traditional BMDMA register, some
methods might not be invoked as expected (e.g. bmdma_stop from
ata_sff_post_internal_cmd()).
p4. SFF drivers w/ custom DMA interface implement noop BMDMA ops
worrying libata core might call into one of them.
These problems are caused by the muddy line between SFF and BMDMA and
the assumption that all BMDMA controllers initialize bmdma_addr.
This patch fixes p1 and p2 by removing the bmdma_addr assumption and
moving prd allocation to BMDMA port start. Later patches will fix the
remaining issues.
This patch improves BMDMA initialization such that
* When BMDMA register initialization fails, falls back to PIO instead
of failing. ata_pci_bmdma_init() never fails now.
* When ata_pci_bmdma_init() falls back to PIO, it clears
ap->mwdma_mask and udma_mask instead of depending on
ata_bmdma_mode_filter(). This makes ata_bmdma_mode_filter()
unnecessary thus resolving p1.
* ata_port_start() which actually is BMDMA specific is moved to
ata_bmdma_port_start(). ata_port_start() and ata_sff_port_start()
are killed.
* ata_sff_port_start32() is moved and renamed to
ata_bmdma_port_start32().
Drivers which no longer call into PRD table allocation are...
pdc_adma, sata_inic162x, sata_qstor, sata_sx4, pata_cmd640 and all
drivers which inherit from ata_sff_port_ops.
pata_icside sets ->port_start to ATA_OP_NULL as it doesn't need PRD
but is a BMDMA controller and doesn't have custom port_start like
other such controllers.
Note that with the previous patch which makes all and only BMDMA
drivers inherit from ata_bmdma_port_ops, this change doesn't break
drivers which need PRD table.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-05-10 13:41:34 -06:00
|
|
|
* Allocate space for PRD table using ata_bmdma_port_start().
|
2007-01-26 00:28:18 -07:00
|
|
|
* Set PRD table address for PTERADD. (PRD Transfer End Read)
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int scc_port_start (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
|
|
|
int rc;
|
|
|
|
|
libata-sff: clean up BMDMA initialization
When BMDMA initialization failed or BMDMA was not available for
whatever reason, bmdma_addr was left at zero and used as an indication
that BMDMA shouldn't be used. This leads to the following problems.
p1. For BMDMA drivers which don't use traditional BMDMA register,
ata_bmdma_mode_filter() incorrectly inhibits DMA modes. Those
drivers either have to inherit from ata_sff_port_ops or clear
->mode_filter explicitly.
p2. non-BMDMA drivers call into BMDMA PRD table allocation. It
doesn't actually allocate PRD table if bmdma_addr is not
initialized but is still confusing.
p3. For BMDMA drivers which don't use traditional BMDMA register, some
methods might not be invoked as expected (e.g. bmdma_stop from
ata_sff_post_internal_cmd()).
p4. SFF drivers w/ custom DMA interface implement noop BMDMA ops
worrying libata core might call into one of them.
These problems are caused by the muddy line between SFF and BMDMA and
the assumption that all BMDMA controllers initialize bmdma_addr.
This patch fixes p1 and p2 by removing the bmdma_addr assumption and
moving prd allocation to BMDMA port start. Later patches will fix the
remaining issues.
This patch improves BMDMA initialization such that
* When BMDMA register initialization fails, falls back to PIO instead
of failing. ata_pci_bmdma_init() never fails now.
* When ata_pci_bmdma_init() falls back to PIO, it clears
ap->mwdma_mask and udma_mask instead of depending on
ata_bmdma_mode_filter(). This makes ata_bmdma_mode_filter()
unnecessary thus resolving p1.
* ata_port_start() which actually is BMDMA specific is moved to
ata_bmdma_port_start(). ata_port_start() and ata_sff_port_start()
are killed.
* ata_sff_port_start32() is moved and renamed to
ata_bmdma_port_start32().
Drivers which no longer call into PRD table allocation are...
pdc_adma, sata_inic162x, sata_qstor, sata_sx4, pata_cmd640 and all
drivers which inherit from ata_sff_port_ops.
pata_icside sets ->port_start to ATA_OP_NULL as it doesn't need PRD
but is a BMDMA controller and doesn't have custom port_start like
other such controllers.
Note that with the previous patch which makes all and only BMDMA
drivers inherit from ata_bmdma_port_ops, this change doesn't break
drivers which need PRD table.
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
2010-05-10 13:41:34 -06:00
|
|
|
rc = ata_bmdma_port_start(ap);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2010-05-10 13:41:41 -06:00
|
|
|
out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
|
2007-01-26 00:28:18 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_port_stop - Undo scc_port_start()
|
|
|
|
* @ap: Port to shut down
|
|
|
|
*
|
|
|
|
* Reset PTERADD.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_port_stop (struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *mmio = ap->ioaddr.bmdma_addr;
|
|
|
|
|
|
|
|
out_be32(mmio + SCC_DMA_PTERADD, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct scsi_host_template scc_sht = {
|
2008-03-24 21:22:49 -06:00
|
|
|
ATA_BMDMA_SHT(DRV_NAME),
|
2007-01-26 00:28:18 -07:00
|
|
|
};
|
|
|
|
|
2008-03-27 04:44:24 -06:00
|
|
|
static struct ata_port_operations scc_pata_ops = {
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-24 21:22:49 -06:00
|
|
|
.inherits = &ata_bmdma_port_ops,
|
|
|
|
|
2007-01-26 00:28:18 -07:00
|
|
|
.set_piomode = scc_set_piomode,
|
|
|
|
.set_dmamode = scc_set_dmamode,
|
2007-07-16 21:10:17 -06:00
|
|
|
.mode_filter = scc_mode_filter,
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
.sff_tf_load = scc_tf_load,
|
|
|
|
.sff_tf_read = scc_tf_read,
|
|
|
|
.sff_exec_command = scc_exec_command,
|
|
|
|
.sff_check_status = scc_check_status,
|
|
|
|
.sff_check_altstatus = scc_check_altstatus,
|
|
|
|
.sff_dev_select = scc_dev_select,
|
2010-05-07 12:47:50 -06:00
|
|
|
.sff_set_devctl = scc_set_devctl,
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
.bmdma_setup = scc_bmdma_setup,
|
|
|
|
.bmdma_start = scc_bmdma_start,
|
|
|
|
.bmdma_stop = scc_bmdma_stop,
|
|
|
|
.bmdma_status = scc_bmdma_status,
|
2008-04-07 07:47:16 -06:00
|
|
|
.sff_data_xfer = scc_data_xfer,
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2011-10-12 09:16:37 -06:00
|
|
|
.cable_detect = ata_cable_80wire,
|
2008-04-07 07:47:16 -06:00
|
|
|
.softreset = scc_softreset,
|
|
|
|
.postreset = scc_postreset,
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2008-04-07 07:47:16 -06:00
|
|
|
.sff_irq_clear = scc_irq_clear,
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
.port_start = scc_port_start,
|
|
|
|
.port_stop = scc_port_stop,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_info scc_port_info[] = {
|
|
|
|
{
|
2011-02-04 12:05:48 -07:00
|
|
|
.flags = ATA_FLAG_SLAVE_POSS,
|
2009-03-14 14:38:24 -06:00
|
|
|
.pio_mask = ATA_PIO4,
|
|
|
|
/* No MWDMA */
|
2007-01-26 00:28:18 -07:00
|
|
|
.udma_mask = ATA_UDMA6,
|
|
|
|
.port_ops = &scc_pata_ops,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_reset_controller - initialize SCC PATA controller.
|
|
|
|
*/
|
|
|
|
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
static int scc_reset_controller(struct ata_host *host)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
|
|
|
|
void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
|
2007-01-26 00:28:18 -07:00
|
|
|
void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
|
|
|
|
void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
|
|
|
|
void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
|
|
|
|
void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
|
|
|
|
void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
|
|
|
|
u32 reg = 0;
|
|
|
|
|
|
|
|
out_be32(cckctrl_port, reg);
|
|
|
|
reg |= CCKCTRL_ATACLKOEN;
|
|
|
|
out_be32(cckctrl_port, reg);
|
|
|
|
reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
|
|
|
|
out_be32(cckctrl_port, reg);
|
|
|
|
reg |= CCKCTRL_CRST;
|
|
|
|
out_be32(cckctrl_port, reg);
|
|
|
|
|
|
|
|
for (;;) {
|
|
|
|
reg = in_be32(cckctrl_port);
|
|
|
|
if (reg & CCKCTRL_CRST)
|
|
|
|
break;
|
|
|
|
udelay(5000);
|
|
|
|
}
|
|
|
|
|
|
|
|
reg |= CCKCTRL_ATARESET;
|
|
|
|
out_be32(cckctrl_port, reg);
|
|
|
|
out_be32(ecmode_port, ECMODE_VALUE);
|
|
|
|
out_be32(mode_port, MODE_JCUSFEN);
|
|
|
|
out_be32(intmask_port, INTMASK_MSK);
|
|
|
|
|
|
|
|
if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
|
|
|
|
printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
|
|
|
|
return -EIO;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
|
|
|
|
* @ioaddr: IO address structure to be initialized
|
|
|
|
* @base: base address of BMID region
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
|
|
|
|
{
|
|
|
|
ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
|
|
|
|
ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
|
|
|
|
ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
|
|
|
|
ioaddr->bmdma_addr = base;
|
|
|
|
ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
|
|
|
|
ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
|
|
|
|
ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
|
|
|
|
ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
|
|
|
|
ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
|
|
|
|
ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
|
|
|
|
ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
|
|
|
|
ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
|
|
|
|
ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
|
|
|
|
ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
|
|
|
|
}
|
|
|
|
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
static int scc_host_init(struct ata_host *host)
|
2007-01-26 00:28:18 -07:00
|
|
|
{
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
struct pci_dev *pdev = to_pci_dev(host->dev);
|
2007-01-26 00:28:18 -07:00
|
|
|
int rc;
|
|
|
|
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
rc = scc_reset_controller(host);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
pci_set_master(pdev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* scc_init_one - Register SCC PATA device with kernel services
|
|
|
|
* @pdev: PCI device to register
|
|
|
|
* @ent: Entry in scc_pci_tbl matching with @pdev
|
|
|
|
*
|
|
|
|
* LOCKING:
|
|
|
|
* Inherited from PCI layer (may sleep).
|
|
|
|
*
|
|
|
|
* RETURNS:
|
|
|
|
* Zero on success, or -ERRNO value.
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
|
unsigned int board_idx = (unsigned int) ent->driver_data;
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
|
2007-05-03 13:44:59 -06:00
|
|
|
struct ata_host *host;
|
2007-01-26 00:28:18 -07:00
|
|
|
int rc;
|
|
|
|
|
2011-04-15 16:52:00 -06:00
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2007-05-03 13:44:59 -06:00
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
if (!host)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2007-01-26 00:28:18 -07:00
|
|
|
rc = pcim_enable_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
|
|
|
|
if (rc == -EBUSY)
|
|
|
|
pcim_pin_device(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
host->iomap = pcim_iomap_table(pdev);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
2007-08-17 22:14:55 -06:00
|
|
|
ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
|
|
|
|
ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
|
|
|
|
|
libata: convert the remaining PATA drivers to new init model
Convert pdc_adma, pata_cs5520, pata_isapnp, pata_ixp4xx_cf,
pata_legacy, pata_mpc52xx, pata_mpiix, pata_pcmcia, pata_pdc2027x,
pata_platform, pata_qdi, pata_scc and pata_winbond to new init model.
* init_one()'s now follow more consistent init order
* cs5520 now registers one host with two ports, not two hosts. If any
of the two ports are disabled, it's made dummy as other drivers do.
Tested pdc_adma and pata_legacy. Both are as broken as before. The
rest are compile tested only.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 08:44:08 -06:00
|
|
|
rc = scc_host_init(host);
|
2007-01-26 00:28:18 -07:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2010-05-19 14:10:21 -06:00
|
|
|
return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
|
2008-04-07 07:47:16 -06:00
|
|
|
IRQF_SHARED, &scc_sht);
|
2007-01-26 00:28:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
static struct pci_driver scc_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = scc_pci_tbl,
|
|
|
|
.probe = scc_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
2014-05-07 09:17:44 -06:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2007-01-26 00:28:18 -07:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = ata_pci_device_resume,
|
|
|
|
#endif
|
|
|
|
};
|
|
|
|
|
2012-04-18 23:43:05 -06:00
|
|
|
module_pci_driver(scc_pci_driver);
|
2007-01-26 00:28:18 -07:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Toshiba corp");
|
|
|
|
MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|