2008-07-24 03:27:36 -06:00
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/*
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* MUSB OTG driver - support for Mentor's DMA controller
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*
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* Copyright 2005 Mentor Graphics Corporation
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* Copyright (C) 2005-2007 by Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include "musb_core.h"
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2008-12-02 12:33:47 -07:00
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#include "musbhsdma.h"
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2008-07-24 03:27:36 -06:00
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static int dma_controller_start(struct dma_controller *c)
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{
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/* nothing to do */
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return 0;
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}
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2008-09-11 02:53:24 -06:00
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static void dma_channel_release(struct dma_channel *channel);
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2008-07-24 03:27:36 -06:00
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static int dma_controller_stop(struct dma_controller *c)
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb *musb = controller->private_data;
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struct dma_channel *channel;
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u8 bit;
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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if (controller->used_channels != 0) {
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2008-07-24 03:27:36 -06:00
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dev_err(musb->controller,
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"Stopping DMA controller while channel active\n");
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2008-09-11 02:53:24 -06:00
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (controller->used_channels & (1 << bit)) {
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channel = &controller->channel[bit].channel;
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dma_channel_release(channel);
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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if (!controller->used_channels)
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2008-07-24 03:27:36 -06:00
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break;
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}
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}
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}
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2008-09-11 02:53:24 -06:00
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2008-07-24 03:27:36 -06:00
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return 0;
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}
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static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
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struct musb_hw_ep *hw_ep, u8 transmit)
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_controller *controller = container_of(c,
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struct musb_dma_controller, controller);
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struct musb_dma_channel *musb_channel = NULL;
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struct dma_channel *channel = NULL;
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u8 bit;
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for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
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if (!(controller->used_channels & (1 << bit))) {
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controller->used_channels |= (1 << bit);
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musb_channel = &(controller->channel[bit]);
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musb_channel->controller = controller;
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musb_channel->idx = bit;
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musb_channel->epnum = hw_ep->epnum;
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musb_channel->transmit = transmit;
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channel = &(musb_channel->channel);
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channel->private_data = musb_channel;
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channel->status = MUSB_DMA_STATUS_FREE;
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channel->max_len = 0x10000;
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2008-07-24 03:27:36 -06:00
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/* Tx => mode 1; Rx => mode 0 */
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2008-09-11 02:53:24 -06:00
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channel->desired_mode = transmit;
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channel->actual_len = 0;
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2008-07-24 03:27:36 -06:00
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break;
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}
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}
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2008-09-11 02:53:24 -06:00
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return channel;
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2008-07-24 03:27:36 -06:00
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}
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2008-09-11 02:53:24 -06:00
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static void dma_channel_release(struct dma_channel *channel)
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2008-07-24 03:27:36 -06:00
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_channel *musb_channel = channel->private_data;
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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channel->actual_len = 0;
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musb_channel->start_addr = 0;
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musb_channel->len = 0;
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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musb_channel->controller->used_channels &=
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~(1 << musb_channel->idx);
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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channel->status = MUSB_DMA_STATUS_UNKNOWN;
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2008-07-24 03:27:36 -06:00
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}
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2008-09-11 02:53:24 -06:00
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static void configure_channel(struct dma_channel *channel,
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2008-07-24 03:27:36 -06:00
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_channel *musb_channel = channel->private_data;
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struct musb_dma_controller *controller = musb_channel->controller;
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void __iomem *mbase = controller->base;
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u8 bchannel = musb_channel->idx;
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2008-07-24 03:27:36 -06:00
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u16 csr = 0;
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DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
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2008-09-11 02:53:24 -06:00
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channel, packet_sz, dma_addr, len, mode);
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2008-07-24 03:27:36 -06:00
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if (mode) {
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csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
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BUG_ON(len < packet_sz);
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if (packet_sz >= 64) {
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csr |= MUSB_HSDMA_BURSTMODE_INCR16
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<< MUSB_HSDMA_BURSTMODE_SHIFT;
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} else if (packet_sz >= 32) {
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csr |= MUSB_HSDMA_BURSTMODE_INCR8
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<< MUSB_HSDMA_BURSTMODE_SHIFT;
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} else if (packet_sz >= 16) {
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csr |= MUSB_HSDMA_BURSTMODE_INCR4
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<< MUSB_HSDMA_BURSTMODE_SHIFT;
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}
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}
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2008-09-11 02:53:24 -06:00
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csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
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2008-07-24 03:27:36 -06:00
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| (1 << MUSB_HSDMA_ENABLE_SHIFT)
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| (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
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2008-09-11 02:53:24 -06:00
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| (musb_channel->transmit
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2008-07-24 03:27:36 -06:00
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? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
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: 0);
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/* address/count */
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2008-12-02 12:33:47 -07:00
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musb_write_hsdma_addr(mbase, bchannel, dma_addr);
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musb_write_hsdma_count(mbase, bchannel, len);
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2008-07-24 03:27:36 -06:00
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/* control (this should start things) */
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musb_writew(mbase,
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2008-09-11 02:53:24 -06:00
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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2008-07-24 03:27:36 -06:00
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csr);
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}
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2008-09-11 02:53:24 -06:00
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static int dma_channel_program(struct dma_channel *channel,
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2008-07-24 03:27:36 -06:00
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u16 packet_sz, u8 mode,
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dma_addr_t dma_addr, u32 len)
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_channel *musb_channel = channel->private_data;
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2008-07-24 03:27:36 -06:00
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DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
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2008-09-11 02:53:24 -06:00
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musb_channel->epnum,
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musb_channel->transmit ? "Tx" : "Rx",
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2008-07-24 03:27:36 -06:00
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packet_sz, dma_addr, len, mode);
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2008-09-11 02:53:24 -06:00
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BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
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channel->status == MUSB_DMA_STATUS_BUSY);
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2008-07-24 03:27:36 -06:00
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2008-09-11 02:53:24 -06:00
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channel->actual_len = 0;
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musb_channel->start_addr = dma_addr;
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musb_channel->len = len;
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musb_channel->max_packet_sz = packet_sz;
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channel->status = MUSB_DMA_STATUS_BUSY;
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2008-07-24 03:27:36 -06:00
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if ((mode == 1) && (len >= packet_sz))
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2008-09-11 02:53:24 -06:00
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configure_channel(channel, packet_sz, 1, dma_addr, len);
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2008-07-24 03:27:36 -06:00
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else
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2008-09-11 02:53:24 -06:00
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configure_channel(channel, packet_sz, 0, dma_addr, len);
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2008-07-24 03:27:36 -06:00
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return true;
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}
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2008-09-11 02:53:24 -06:00
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static int dma_channel_abort(struct dma_channel *channel)
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2008-07-24 03:27:36 -06:00
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_channel *musb_channel = channel->private_data;
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void __iomem *mbase = musb_channel->controller->base;
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u8 bchannel = musb_channel->idx;
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2009-03-26 19:27:47 -06:00
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int offset;
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2008-07-24 03:27:36 -06:00
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u16 csr;
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2008-09-11 02:53:24 -06:00
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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if (musb_channel->transmit) {
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2009-03-26 19:27:47 -06:00
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offset = MUSB_EP_OFFSET(musb_channel->epnum,
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MUSB_TXCSR);
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/*
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* The programming guide says that we must clear
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* the DMAENAB bit before the DMAMODE bit...
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*/
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csr = musb_readw(mbase, offset);
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csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
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musb_writew(mbase, offset, csr);
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csr &= ~MUSB_TXCSR_DMAMODE;
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musb_writew(mbase, offset, csr);
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2008-07-24 03:27:36 -06:00
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} else {
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2009-03-26 19:27:47 -06:00
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offset = MUSB_EP_OFFSET(musb_channel->epnum,
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MUSB_RXCSR);
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csr = musb_readw(mbase, offset);
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2008-07-24 03:27:36 -06:00
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csr &= ~(MUSB_RXCSR_AUTOCLEAR |
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MUSB_RXCSR_DMAENAB |
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MUSB_RXCSR_DMAMODE);
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2009-03-26 19:27:47 -06:00
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musb_writew(mbase, offset, csr);
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2008-07-24 03:27:36 -06:00
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}
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musb_writew(mbase,
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2008-09-11 02:53:24 -06:00
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
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2008-07-24 03:27:36 -06:00
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0);
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2008-12-02 12:33:47 -07:00
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musb_write_hsdma_addr(mbase, bchannel, 0);
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musb_write_hsdma_count(mbase, bchannel, 0);
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2008-09-11 02:53:24 -06:00
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channel->status = MUSB_DMA_STATUS_FREE;
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2008-07-24 03:27:36 -06:00
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}
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2008-09-11 02:53:24 -06:00
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2008-07-24 03:27:36 -06:00
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return 0;
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}
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static irqreturn_t dma_controller_irq(int irq, void *private_data)
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{
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2008-09-11 02:53:24 -06:00
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struct musb_dma_controller *controller = private_data;
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struct musb *musb = controller->private_data;
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struct musb_dma_channel *musb_channel;
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struct dma_channel *channel;
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void __iomem *mbase = controller->base;
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|
2008-07-24 03:27:36 -06:00
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irqreturn_t retval = IRQ_NONE;
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2008-09-11 02:53:24 -06:00
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2008-07-24 03:27:36 -06:00
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unsigned long flags;
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2008-09-11 02:53:24 -06:00
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u8 bchannel;
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u8 int_hsdma;
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2009-12-28 04:40:36 -07:00
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u32 addr, count;
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2008-09-11 02:53:24 -06:00
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u16 csr;
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2008-07-24 03:27:36 -06:00
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spin_lock_irqsave(&musb->lock, flags);
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int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
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2009-11-16 03:49:26 -07:00
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#ifdef CONFIG_BLACKFIN
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/* Clear DMA interrupt flags */
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musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
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#endif
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2009-12-28 04:40:36 -07:00
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if (!int_hsdma) {
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DBG(2, "spurious DMA irq\n");
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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if (channel->status == MUSB_DMA_STATUS_BUSY) {
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count = musb_read_hsdma_count(mbase, bchannel);
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if (count == 0)
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int_hsdma |= (1 << bchannel);
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}
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}
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DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
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if (!int_hsdma)
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goto done;
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}
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|
2008-09-11 02:53:24 -06:00
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for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
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if (int_hsdma & (1 << bchannel)) {
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musb_channel = (struct musb_dma_channel *)
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&(controller->channel[bchannel]);
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channel = &musb_channel->channel;
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2008-07-24 03:27:36 -06:00
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csr = musb_readw(mbase,
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2008-09-11 02:53:24 -06:00
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MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
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2008-07-24 03:27:36 -06:00
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MUSB_HSDMA_CONTROL));
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2008-09-11 02:53:24 -06:00
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if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
|
|
|
|
musb_channel->channel.status =
|
2008-07-24 03:27:36 -06:00
|
|
|
MUSB_DMA_STATUS_BUS_ABORT;
|
2008-09-11 02:53:24 -06:00
|
|
|
} else {
|
2008-07-24 03:27:36 -06:00
|
|
|
u8 devctl;
|
|
|
|
|
2008-12-02 12:33:47 -07:00
|
|
|
addr = musb_read_hsdma_addr(mbase,
|
|
|
|
bchannel);
|
2008-09-11 02:53:24 -06:00
|
|
|
channel->actual_len = addr
|
|
|
|
- musb_channel->start_addr;
|
2008-07-24 03:27:36 -06:00
|
|
|
|
2009-11-16 03:49:29 -07:00
|
|
|
DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
|
2008-09-11 02:53:24 -06:00
|
|
|
channel, musb_channel->start_addr,
|
|
|
|
addr, channel->actual_len,
|
|
|
|
musb_channel->len,
|
|
|
|
(channel->actual_len
|
|
|
|
< musb_channel->len) ?
|
2008-07-24 03:27:36 -06:00
|
|
|
"=> reconfig 0" : "=> complete");
|
|
|
|
|
|
|
|
devctl = musb_readb(mbase, MUSB_DEVCTL);
|
|
|
|
|
2008-09-11 02:53:24 -06:00
|
|
|
channel->status = MUSB_DMA_STATUS_FREE;
|
2008-07-24 03:27:36 -06:00
|
|
|
|
|
|
|
/* completed */
|
|
|
|
if ((devctl & MUSB_DEVCTL_HM)
|
2008-09-11 02:53:24 -06:00
|
|
|
&& (musb_channel->transmit)
|
|
|
|
&& ((channel->desired_mode == 0)
|
|
|
|
|| (channel->actual_len &
|
|
|
|
(musb_channel->max_packet_sz - 1)))
|
2009-03-26 19:27:47 -06:00
|
|
|
) {
|
|
|
|
u8 epnum = musb_channel->epnum;
|
|
|
|
int offset = MUSB_EP_OFFSET(epnum,
|
|
|
|
MUSB_TXCSR);
|
|
|
|
u16 txcsr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The programming guide says that we
|
|
|
|
* must clear DMAENAB before DMAMODE.
|
|
|
|
*/
|
|
|
|
musb_ep_select(mbase, epnum);
|
|
|
|
txcsr = musb_readw(mbase, offset);
|
|
|
|
txcsr &= ~(MUSB_TXCSR_DMAENAB
|
|
|
|
| MUSB_TXCSR_AUTOSET);
|
|
|
|
musb_writew(mbase, offset, txcsr);
|
2008-07-24 03:27:36 -06:00
|
|
|
/* Send out the packet */
|
2009-03-26 19:27:47 -06:00
|
|
|
txcsr &= ~MUSB_TXCSR_DMAMODE;
|
|
|
|
txcsr |= MUSB_TXCSR_TXPKTRDY;
|
|
|
|
musb_writew(mbase, offset, txcsr);
|
2008-09-11 02:53:24 -06:00
|
|
|
}
|
USB: musb: bugfixes for multi-packet TXDMA support
We really want to use DMA mode 1 for all multi-packet transfers;
that's one IRQ on DMA completion, instead of one per packet.
There is an important issue with such transfers, especially on
the host side: when such transfers end with a full-size packet,
we must defer musb_dma_completion() calls until the FIFO empties.
Else we report URB completions too soon, and may clobber data in
the FIFO fifo when writing the next packet (losing data).
The Inventra DMA support uses DMA mode 1, but it ignores that
issue. The CPPI DMA support uses mode 0, but doesn't handle
its TXPKTRDY interrupts quite right either; it can get stale
"packet ready" interrupts, and report transfer completion too
early using slightly different code paths, also losing data.
So I'm solving it in a generic way -- by adding a sort of the
"interrupt filter" into musb_host_tx(), catching these cases
where a DMA completion IRQ doesn't suffice and removing some
needlessly controller-specific logic. When a TXDMA interrupt
happens and DMA request mode 1 is active, that filter resets
to mode 0 and defers URB completion processing until TXPKTRDY,
unless the FIFO is already empty. Related filtering logic in
Inventra and CPPI code gets removed.
Since it should be competely safe now to use the DMA request
mode 1 for host side transfers with the CPPI DMA controller,
set it in musb_h_tx_dma_start() ... now renamed (and shared).
[ dbrownell@users.sourceforge.net: don't introduce more
CamElCase; use more concise explanations ]
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-03-26 19:26:40 -06:00
|
|
|
musb_dma_completion(musb, musb_channel->epnum,
|
|
|
|
musb_channel->transmit);
|
2008-07-24 03:27:36 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2008-12-02 12:33:47 -07:00
|
|
|
|
2008-07-24 03:27:36 -06:00
|
|
|
retval = IRQ_HANDLED;
|
|
|
|
done:
|
|
|
|
spin_unlock_irqrestore(&musb->lock, flags);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
void dma_controller_destroy(struct dma_controller *c)
|
|
|
|
{
|
2008-09-11 02:53:24 -06:00
|
|
|
struct musb_dma_controller *controller = container_of(c,
|
|
|
|
struct musb_dma_controller, controller);
|
2008-07-24 03:27:36 -06:00
|
|
|
|
|
|
|
if (!controller)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (controller->irq)
|
|
|
|
free_irq(controller->irq, c);
|
|
|
|
|
|
|
|
kfree(controller);
|
|
|
|
}
|
|
|
|
|
|
|
|
struct dma_controller *__init
|
2008-09-11 02:53:24 -06:00
|
|
|
dma_controller_create(struct musb *musb, void __iomem *base)
|
2008-07-24 03:27:36 -06:00
|
|
|
{
|
|
|
|
struct musb_dma_controller *controller;
|
|
|
|
struct device *dev = musb->controller;
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
int irq = platform_get_irq(pdev, 1);
|
|
|
|
|
|
|
|
if (irq == 0) {
|
|
|
|
dev_err(dev, "No DMA interrupt line!\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2008-09-11 02:53:24 -06:00
|
|
|
controller = kzalloc(sizeof(*controller), GFP_KERNEL);
|
2008-07-24 03:27:36 -06:00
|
|
|
if (!controller)
|
|
|
|
return NULL;
|
|
|
|
|
2008-09-11 02:53:24 -06:00
|
|
|
controller->channel_count = MUSB_HSDMA_CHANNELS;
|
|
|
|
controller->private_data = musb;
|
|
|
|
controller->base = base;
|
2008-07-24 03:27:36 -06:00
|
|
|
|
2008-09-11 02:53:24 -06:00
|
|
|
controller->controller.start = dma_controller_start;
|
|
|
|
controller->controller.stop = dma_controller_stop;
|
|
|
|
controller->controller.channel_alloc = dma_channel_allocate;
|
|
|
|
controller->controller.channel_release = dma_channel_release;
|
|
|
|
controller->controller.channel_program = dma_channel_program;
|
|
|
|
controller->controller.channel_abort = dma_channel_abort;
|
2008-07-24 03:27:36 -06:00
|
|
|
|
|
|
|
if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
|
2008-11-06 17:52:53 -07:00
|
|
|
dev_name(musb->controller), &controller->controller)) {
|
2008-07-24 03:27:36 -06:00
|
|
|
dev_err(dev, "request_irq %d failed!\n", irq);
|
2008-09-11 02:53:24 -06:00
|
|
|
dma_controller_destroy(&controller->controller);
|
|
|
|
|
2008-07-24 03:27:36 -06:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
controller->irq = irq;
|
|
|
|
|
2008-09-11 02:53:24 -06:00
|
|
|
return &controller->controller;
|
2008-07-24 03:27:36 -06:00
|
|
|
}
|