2009-08-20 19:23:41 -06:00
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/*
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* ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
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*
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* Copyright (C) 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on wm8731.c by Richard Purdie
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* Based on ak4535.c by Richard Purdie
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* Based on wm8753.c by Liam Girdwood
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* ** CAUTION **
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*
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* This is very simple driver.
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* It can use headphone output / stereo input only
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*
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2011-11-06 23:04:53 -07:00
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* AK4642 is tested.
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2009-08-20 19:23:41 -06:00
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* AK4643 is tested.
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2011-11-10 17:22:05 -07:00
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* AK4648 is tested.
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2009-08-20 19:23:41 -06:00
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*/
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2015-09-10 00:40:19 -06:00
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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2009-08-20 19:23:41 -06:00
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#include <linux/delay.h>
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#include <linux/i2c.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2013-01-10 01:29:11 -07:00
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#include <linux/of_device.h>
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2011-07-15 10:38:28 -06:00
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#include <linux/module.h>
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2013-11-28 11:03:49 -07:00
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#include <linux/regmap.h>
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2010-11-05 07:53:46 -06:00
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#include <sound/soc.h>
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2009-08-20 19:23:41 -06:00
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#include <sound/initval.h>
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2010-06-30 23:23:45 -06:00
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#include <sound/tlv.h>
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2009-08-20 19:23:41 -06:00
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#define PW_MGMT1 0x00
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#define PW_MGMT2 0x01
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#define SG_SL1 0x02
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#define SG_SL2 0x03
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#define MD_CTL1 0x04
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#define MD_CTL2 0x05
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#define TIMER 0x06
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#define ALC_CTL1 0x07
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#define ALC_CTL2 0x08
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#define L_IVC 0x09
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#define L_DVC 0x0a
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#define ALC_CTL3 0x0b
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#define R_IVC 0x0c
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#define R_DVC 0x0d
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#define MD_CTL3 0x0e
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#define MD_CTL4 0x0f
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#define PW_MGMT3 0x10
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#define DF_S 0x11
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#define FIL3_0 0x12
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#define FIL3_1 0x13
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#define FIL3_2 0x14
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#define FIL3_3 0x15
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#define EQ_0 0x16
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#define EQ_1 0x17
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#define EQ_2 0x18
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#define EQ_3 0x19
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#define EQ_4 0x1a
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#define EQ_5 0x1b
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#define FIL1_0 0x1c
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#define FIL1_1 0x1d
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#define FIL1_2 0x1e
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2015-06-30 10:56:36 -06:00
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#define FIL1_3 0x1f /* The maximum valid register for ak4642 */
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2009-08-20 19:23:41 -06:00
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#define PW_MGMT4 0x20
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#define MD_CTL5 0x21
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#define LO_MS 0x22
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#define HP_MS 0x23
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2015-06-30 10:56:36 -06:00
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#define SPK_MS 0x24 /* The maximum valid register for ak4643 */
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#define EQ_FBEQAB 0x25
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#define EQ_FBEQCD 0x26
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#define EQ_FBEQE 0x27 /* The maximum valid register for ak4648 */
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2009-08-20 19:23:41 -06:00
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2010-10-14 23:23:18 -06:00
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/* PW_MGMT1*/
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#define PMVCM (1 << 6) /* VCOM Power Management */
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#define PMMIN (1 << 5) /* MIN Input Power Management */
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#define PMDAC (1 << 2) /* DAC Power Management */
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#define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
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2010-03-15 03:10:50 -06:00
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/* PW_MGMT2 */
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#define HPMTN (1 << 6)
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#define PMHPL (1 << 5)
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#define PMHPR (1 << 4)
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#define MS (1 << 3) /* master/slave select */
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#define MCKO (1 << 1)
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#define PMPLL (1 << 0)
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#define PMHP_MASK (PMHPL | PMHPR)
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#define PMHP PMHP_MASK
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2010-10-14 23:23:18 -06:00
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/* PW_MGMT3 */
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#define PMADR (1 << 0) /* MIC L / ADC R Power Management */
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/* SG_SL1 */
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#define MINS (1 << 6) /* Switch from MIN to Speaker */
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#define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
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#define PMMP (1 << 2) /* MPWR pin Power Management */
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#define MGAIN0 (1 << 0) /* MIC amp gain*/
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2015-03-23 23:15:22 -06:00
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/* SG_SL2 */
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#define LOPS (1 << 6) /* Stero Line-out Power Save Mode */
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2010-10-14 23:23:18 -06:00
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/* TIMER */
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2014-05-14 01:37:33 -06:00
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#define ZTM(param) ((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
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2010-10-14 23:23:18 -06:00
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#define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
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/* ALC_CTL1 */
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#define ALC (1 << 5) /* ALC Enable */
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#define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
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2010-03-23 01:27:28 -06:00
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/* MD_CTL1 */
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#define PLL3 (1 << 7)
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#define PLL2 (1 << 6)
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#define PLL1 (1 << 5)
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#define PLL0 (1 << 4)
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#define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
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2010-03-15 03:10:50 -06:00
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#define BCKO_MASK (1 << 3)
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#define BCKO_64 BCKO_MASK
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2011-01-19 19:45:34 -07:00
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#define DIF_MASK (3 << 0)
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#define DSP (0 << 0)
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#define RIGHT_J (1 << 0)
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#define LEFT_J (2 << 0)
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#define I2S (3 << 0)
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2010-03-23 01:27:38 -06:00
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/* MD_CTL2 */
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2015-09-14 20:42:42 -06:00
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#define FSs(val) (((val & 0x7) << 0) | ((val & 0x8) << 2))
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#define PSs(val) ((val & 0x3) << 6)
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2010-03-23 01:27:38 -06:00
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2010-10-14 23:23:18 -06:00
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/* MD_CTL3 */
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#define BST1 (1 << 3)
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/* MD_CTL4 */
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#define DACH (1 << 0)
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2009-08-20 19:23:41 -06:00
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2014-05-14 01:37:35 -06:00
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struct ak4642_drvdata {
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const struct regmap_config *regmap_config;
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2014-05-14 01:37:36 -06:00
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int extended_frequencies;
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2014-05-14 01:37:35 -06:00
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};
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struct ak4642_priv {
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const struct ak4642_drvdata *drvdata;
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2015-09-10 00:40:19 -06:00
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struct clk *mcko;
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2014-05-14 01:37:35 -06:00
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};
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2010-06-30 23:23:45 -06:00
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/*
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* Playback Volume (table 39)
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*
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* max : 0x00 : +12.0 dB
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* ( 0.5 dB step )
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* min : 0xFE : -115.0 dB
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* mute: 0xFF
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*/
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2012-04-05 00:28:01 -06:00
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static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
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2010-06-30 23:23:45 -06:00
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static const struct snd_kcontrol_new ak4642_snd_controls[] = {
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SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
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0, 0xFF, 1, out_tlv),
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2014-05-14 01:37:34 -06:00
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SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
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SOC_SINGLE("ALC Capture ZC Switch", ALC_CTL1, 4, 1, 1),
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2010-06-30 23:23:45 -06:00
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};
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2012-02-20 21:14:16 -07:00
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static const struct snd_kcontrol_new ak4642_headphone_control =
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SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
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2011-11-10 17:21:31 -07:00
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2011-11-10 17:21:55 -07:00
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static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
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SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
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};
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2015-03-23 23:15:22 -06:00
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/* event handlers */
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static int ak4642_lout_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMD:
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case SND_SOC_DAPM_PRE_PMU:
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/* Power save mode ON */
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snd_soc_update_bits(codec, SG_SL2, LOPS, LOPS);
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break;
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case SND_SOC_DAPM_POST_PMU:
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case SND_SOC_DAPM_POST_PMD:
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/* Power save mode OFF */
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mdelay(300);
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snd_soc_update_bits(codec, SG_SL2, LOPS, 0);
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break;
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}
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return 0;
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}
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2011-11-10 17:21:31 -07:00
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static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
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/* Outputs */
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SND_SOC_DAPM_OUTPUT("HPOUTL"),
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SND_SOC_DAPM_OUTPUT("HPOUTR"),
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2011-11-10 17:21:55 -07:00
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SND_SOC_DAPM_OUTPUT("LINEOUT"),
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2011-11-10 17:21:31 -07:00
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2012-02-20 21:14:16 -07:00
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SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
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SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
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SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
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&ak4642_headphone_control),
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2011-11-10 17:21:31 -07:00
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2012-02-20 21:14:16 -07:00
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SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
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2011-11-10 17:21:31 -07:00
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2015-03-23 23:15:22 -06:00
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SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
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2011-11-10 17:21:55 -07:00
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&ak4642_lout_mixer_controls[0],
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2015-03-23 23:15:22 -06:00
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ARRAY_SIZE(ak4642_lout_mixer_controls),
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ak4642_lout_event,
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SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
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SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
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2011-11-10 17:21:55 -07:00
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2011-11-10 17:21:31 -07:00
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/* DAC */
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2015-03-15 22:45:54 -06:00
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SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
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2011-11-10 17:21:31 -07:00
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};
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static const struct snd_soc_dapm_route ak4642_intercon[] = {
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/* Outputs */
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2012-02-20 21:14:16 -07:00
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{"HPOUTL", NULL, "HPL Out"},
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{"HPOUTR", NULL, "HPR Out"},
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2011-11-10 17:21:55 -07:00
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{"LINEOUT", NULL, "LINEOUT Mixer"},
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2011-11-10 17:21:31 -07:00
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2012-02-20 21:14:16 -07:00
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{"HPL Out", NULL, "Headphone Enable"},
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{"HPR Out", NULL, "Headphone Enable"},
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{"Headphone Enable", "Switch", "DACH"},
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{"DACH", NULL, "DAC"},
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2011-11-10 17:21:55 -07:00
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{"LINEOUT Mixer", "DACL", "DAC"},
|
2015-03-15 22:45:54 -06:00
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{ "DAC", NULL, "Playback" },
|
2011-11-10 17:21:31 -07:00
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};
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2010-06-30 23:23:45 -06:00
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2009-08-20 19:23:41 -06:00
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/*
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* ak4642 register cache
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*/
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2015-06-30 10:56:36 -06:00
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static const struct reg_default ak4643_reg[] = {
|
2013-11-28 11:03:49 -07:00
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{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
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{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
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{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
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{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
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{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
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|
|
|
{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
|
|
|
|
{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
|
|
|
|
{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
|
|
|
|
{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
|
|
|
|
{ 36, 0x00 },
|
2009-08-20 19:23:41 -06:00
|
|
|
};
|
|
|
|
|
2015-06-30 10:56:36 -06:00
|
|
|
/* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
|
|
|
|
and ak4643. So we reuse the ak4643 reg_default for ak4642.
|
|
|
|
The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
|
|
|
|
so define NUM_AK4642_REG_DEFAULTS for ak4642.
|
|
|
|
*/
|
|
|
|
#define ak4642_reg ak4643_reg
|
|
|
|
#define NUM_AK4642_REG_DEFAULTS (FIL1_3 + 1)
|
|
|
|
|
2013-11-28 11:03:49 -07:00
|
|
|
static const struct reg_default ak4648_reg[] = {
|
|
|
|
{ 0, 0x00 }, { 1, 0x00 }, { 2, 0x01 }, { 3, 0x00 },
|
|
|
|
{ 4, 0x02 }, { 5, 0x00 }, { 6, 0x00 }, { 7, 0x00 },
|
|
|
|
{ 8, 0xe1 }, { 9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
|
|
|
|
{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
|
|
|
|
{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
|
|
|
|
{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
|
|
|
|
{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
|
|
|
|
{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
|
|
|
|
{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
|
|
|
|
{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
|
2011-11-10 17:22:05 -07:00
|
|
|
};
|
|
|
|
|
2009-08-20 19:23:41 -06:00
|
|
|
static int ak4642_dai_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
|
|
|
|
|
|
if (is_play) {
|
|
|
|
/*
|
|
|
|
* start headphone output
|
|
|
|
*
|
|
|
|
* PLL, Master Mode
|
|
|
|
* Audio I/F Format :MSB justified (ADC & DAC)
|
|
|
|
* Bass Boost Level : Middle
|
|
|
|
*
|
|
|
|
* This operation came from example code of
|
|
|
|
* "ASAHI KASEI AK4642" (japanese) manual p97.
|
|
|
|
*/
|
2011-10-11 06:20:53 -06:00
|
|
|
snd_soc_write(codec, L_IVC, 0x91); /* volume */
|
|
|
|
snd_soc_write(codec, R_IVC, 0x91); /* volume */
|
2009-08-20 19:23:41 -06:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* start stereo input
|
|
|
|
*
|
|
|
|
* PLL Master Mode
|
|
|
|
* Audio I/F Format:MSB justified (ADC & DAC)
|
|
|
|
* Pre MIC AMP:+20dB
|
|
|
|
* MIC Power On
|
|
|
|
* ALC setting:Refer to Table 35
|
|
|
|
* ALC bit=“1”
|
|
|
|
*
|
|
|
|
* This operation came from example code of
|
|
|
|
* "ASAHI KASEI AK4642" (japanese) manual p94.
|
|
|
|
*/
|
2013-11-01 00:06:17 -06:00
|
|
|
snd_soc_update_bits(codec, SG_SL1, PMMP | MGAIN0, PMMP | MGAIN0);
|
2011-10-11 06:20:53 -06:00
|
|
|
snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
|
|
|
|
snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
|
2011-11-10 17:21:01 -07:00
|
|
|
snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
|
2010-10-14 23:23:18 -06:00
|
|
|
snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
|
2009-08-20 19:23:41 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
|
|
|
|
|
|
if (is_play) {
|
|
|
|
} else {
|
|
|
|
/* stop stereo input */
|
2010-10-14 23:23:18 -06:00
|
|
|
snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
|
|
|
|
snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
|
|
|
|
snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
|
2009-08-20 19:23:41 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
|
|
|
|
int clk_id, unsigned int freq, int dir)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = codec_dai->codec;
|
2014-05-14 01:37:36 -06:00
|
|
|
struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
|
2010-03-23 01:27:28 -06:00
|
|
|
u8 pll;
|
2014-05-14 01:37:36 -06:00
|
|
|
int extended_freq = 0;
|
2010-03-23 01:27:28 -06:00
|
|
|
|
|
|
|
switch (freq) {
|
|
|
|
case 11289600:
|
|
|
|
pll = PLL2;
|
|
|
|
break;
|
|
|
|
case 12288000:
|
|
|
|
pll = PLL2 | PLL0;
|
|
|
|
break;
|
|
|
|
case 12000000:
|
|
|
|
pll = PLL2 | PLL1;
|
|
|
|
break;
|
|
|
|
case 24000000:
|
|
|
|
pll = PLL2 | PLL1 | PLL0;
|
|
|
|
break;
|
|
|
|
case 13500000:
|
|
|
|
pll = PLL3 | PLL2;
|
|
|
|
break;
|
|
|
|
case 27000000:
|
|
|
|
pll = PLL3 | PLL2 | PLL0;
|
|
|
|
break;
|
2014-05-14 01:37:36 -06:00
|
|
|
case 19200000:
|
|
|
|
pll = PLL3;
|
|
|
|
extended_freq = 1;
|
|
|
|
break;
|
|
|
|
case 13000000:
|
|
|
|
pll = PLL3 | PLL2 | PLL1;
|
|
|
|
extended_freq = 1;
|
|
|
|
break;
|
|
|
|
case 26000000:
|
|
|
|
pll = PLL3 | PLL2 | PLL1 | PLL0;
|
|
|
|
extended_freq = 1;
|
|
|
|
break;
|
2010-03-23 01:27:28 -06:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2014-05-14 01:37:36 -06:00
|
|
|
|
|
|
|
if (extended_freq && !priv->drvdata->extended_frequencies)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2010-03-23 01:27:28 -06:00
|
|
|
snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
|
2009-08-20 19:23:41 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-15 03:10:50 -06:00
|
|
|
static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
|
|
|
u8 data;
|
|
|
|
u8 bcko;
|
|
|
|
|
|
|
|
data = MCKO | PMPLL; /* use MCKO */
|
|
|
|
bcko = 0;
|
|
|
|
|
|
|
|
/* set master/slave audio interface */
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
data |= MS;
|
|
|
|
bcko = BCKO_64;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-07-06 18:58:56 -06:00
|
|
|
snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
|
2010-03-15 03:10:50 -06:00
|
|
|
snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
|
|
|
|
|
2011-01-19 19:45:34 -07:00
|
|
|
/* format type */
|
|
|
|
data = 0;
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_LEFT_J:
|
|
|
|
data = LEFT_J;
|
|
|
|
break;
|
|
|
|
case SND_SOC_DAIFMT_I2S:
|
|
|
|
data = I2S;
|
|
|
|
break;
|
|
|
|
/* FIXME
|
|
|
|
* Please add RIGHT_J / DSP support here
|
|
|
|
*/
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
|
|
|
|
|
2010-03-15 03:10:50 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-09-10 00:40:19 -06:00
|
|
|
static int ak4642_set_mcko(struct snd_soc_codec *codec,
|
|
|
|
u32 frequency)
|
|
|
|
{
|
|
|
|
u32 fs_list[] = {
|
|
|
|
[0] = 8000,
|
|
|
|
[1] = 12000,
|
|
|
|
[2] = 16000,
|
|
|
|
[3] = 24000,
|
|
|
|
[4] = 7350,
|
|
|
|
[5] = 11025,
|
|
|
|
[6] = 14700,
|
|
|
|
[7] = 22050,
|
|
|
|
[10] = 32000,
|
|
|
|
[11] = 48000,
|
|
|
|
[14] = 29400,
|
|
|
|
[15] = 44100,
|
|
|
|
};
|
|
|
|
u32 ps_list[] = {
|
|
|
|
[0] = 256,
|
|
|
|
[1] = 128,
|
|
|
|
[2] = 64,
|
|
|
|
[3] = 32
|
|
|
|
};
|
|
|
|
int ps, fs;
|
|
|
|
|
|
|
|
for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {
|
|
|
|
for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {
|
|
|
|
if (frequency == ps_list[ps] * fs_list[fs]) {
|
2015-09-14 20:42:42 -06:00
|
|
|
snd_soc_write(codec, MD_CTL2,
|
|
|
|
PSs(ps) | FSs(fs));
|
2015-09-10 00:40:19 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-23 01:27:38 -06:00
|
|
|
static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct snd_soc_codec *codec = dai->codec;
|
2015-09-10 00:40:19 -06:00
|
|
|
struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
|
|
|
|
u32 rate = clk_get_rate(priv->mcko);
|
2010-03-23 01:27:38 -06:00
|
|
|
|
2015-09-10 00:40:19 -06:00
|
|
|
if (!rate)
|
|
|
|
rate = params_rate(params) * 256;
|
2009-08-20 19:23:41 -06:00
|
|
|
|
2015-09-10 00:40:19 -06:00
|
|
|
return ak4642_set_mcko(codec, rate);
|
2009-08-20 19:23:41 -06:00
|
|
|
}
|
|
|
|
|
2011-11-10 17:21:01 -07:00
|
|
|
static int ak4642_set_bias_level(struct snd_soc_codec *codec,
|
|
|
|
enum snd_soc_bias_level level)
|
|
|
|
{
|
|
|
|
switch (level) {
|
|
|
|
case SND_SOC_BIAS_OFF:
|
|
|
|
snd_soc_write(codec, PW_MGMT1, 0x00);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-23 03:40:40 -07:00
|
|
|
static const struct snd_soc_dai_ops ak4642_dai_ops = {
|
2009-08-20 19:23:41 -06:00
|
|
|
.startup = ak4642_dai_startup,
|
|
|
|
.shutdown = ak4642_dai_shutdown,
|
|
|
|
.set_sysclk = ak4642_dai_set_sysclk,
|
2010-03-15 03:10:50 -06:00
|
|
|
.set_fmt = ak4642_dai_set_fmt,
|
2010-03-23 01:27:38 -06:00
|
|
|
.hw_params = ak4642_dai_hw_params,
|
2009-08-20 19:23:41 -06:00
|
|
|
};
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_driver ak4642_dai = {
|
|
|
|
.name = "ak4642-hifi",
|
2009-08-20 19:23:41 -06:00
|
|
|
.playback = {
|
|
|
|
.stream_name = "Playback",
|
2015-04-10 02:46:22 -06:00
|
|
|
.channels_min = 2,
|
2009-08-20 19:23:41 -06:00
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE },
|
|
|
|
.capture = {
|
|
|
|
.stream_name = "Capture",
|
2015-04-10 02:46:22 -06:00
|
|
|
.channels_min = 2,
|
2009-08-20 19:23:41 -06:00
|
|
|
.channels_max = 2,
|
|
|
|
.rates = SNDRV_PCM_RATE_8000_48000,
|
|
|
|
.formats = SNDRV_PCM_FMTBIT_S16_LE },
|
|
|
|
.ops = &ak4642_dai_ops,
|
2010-03-23 01:27:38 -06:00
|
|
|
.symmetric_rates = 1,
|
2009-08-20 19:23:41 -06:00
|
|
|
};
|
|
|
|
|
2016-05-31 04:34:59 -06:00
|
|
|
static int ak4642_suspend(struct snd_soc_codec *codec)
|
2009-08-20 19:23:41 -06:00
|
|
|
{
|
2013-11-28 11:03:49 -07:00
|
|
|
struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
|
|
|
|
|
2016-05-31 04:34:59 -06:00
|
|
|
regcache_cache_only(regmap, true);
|
2013-11-28 11:03:49 -07:00
|
|
|
regcache_mark_dirty(regmap);
|
2009-08-20 19:23:41 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-31 04:34:59 -06:00
|
|
|
static int ak4642_resume(struct snd_soc_codec *codec)
|
|
|
|
{
|
|
|
|
struct regmap *regmap = dev_get_regmap(codec->dev, NULL);
|
|
|
|
|
|
|
|
regcache_cache_only(regmap, false);
|
|
|
|
regcache_sync(regmap);
|
|
|
|
return 0;
|
|
|
|
}
|
2015-09-10 00:40:19 -06:00
|
|
|
static int ak4642_probe(struct snd_soc_codec *codec)
|
|
|
|
{
|
|
|
|
struct ak4642_priv *priv = snd_soc_codec_get_drvdata(codec);
|
|
|
|
|
|
|
|
if (priv->mcko)
|
|
|
|
ak4642_set_mcko(codec, clk_get_rate(priv->mcko));
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
|
2015-09-10 00:40:19 -06:00
|
|
|
.probe = ak4642_probe,
|
2016-05-31 04:34:59 -06:00
|
|
|
.suspend = ak4642_suspend,
|
2010-09-15 22:06:40 -06:00
|
|
|
.resume = ak4642_resume,
|
2011-11-10 17:21:01 -07:00
|
|
|
.set_bias_level = ak4642_set_bias_level,
|
2016-08-08 03:06:14 -06:00
|
|
|
.component_driver = {
|
|
|
|
.controls = ak4642_snd_controls,
|
|
|
|
.num_controls = ARRAY_SIZE(ak4642_snd_controls),
|
|
|
|
.dapm_widgets = ak4642_dapm_widgets,
|
|
|
|
.num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
|
|
|
|
.dapm_routes = ak4642_intercon,
|
|
|
|
.num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
|
|
|
|
},
|
2011-11-10 17:22:05 -07:00
|
|
|
};
|
|
|
|
|
2013-11-28 11:03:49 -07:00
|
|
|
static const struct regmap_config ak4642_regmap = {
|
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
2015-06-30 10:56:36 -06:00
|
|
|
.max_register = FIL1_3,
|
2013-11-28 11:03:49 -07:00
|
|
|
.reg_defaults = ak4642_reg,
|
2015-06-30 10:56:36 -06:00
|
|
|
.num_reg_defaults = NUM_AK4642_REG_DEFAULTS,
|
2016-05-18 11:30:39 -06:00
|
|
|
.cache_type = REGCACHE_RBTREE,
|
2015-06-30 10:56:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_config ak4643_regmap = {
|
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
|
|
|
.max_register = SPK_MS,
|
|
|
|
.reg_defaults = ak4643_reg,
|
|
|
|
.num_reg_defaults = ARRAY_SIZE(ak4643_reg),
|
2016-05-18 11:30:39 -06:00
|
|
|
.cache_type = REGCACHE_RBTREE,
|
2013-11-28 11:03:49 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct regmap_config ak4648_regmap = {
|
|
|
|
.reg_bits = 8,
|
|
|
|
.val_bits = 8,
|
2015-06-30 10:56:36 -06:00
|
|
|
.max_register = EQ_FBEQE,
|
2013-11-28 11:03:49 -07:00
|
|
|
.reg_defaults = ak4648_reg,
|
|
|
|
.num_reg_defaults = ARRAY_SIZE(ak4648_reg),
|
2016-05-18 11:30:39 -06:00
|
|
|
.cache_type = REGCACHE_RBTREE,
|
2010-03-17 14:15:21 -06:00
|
|
|
};
|
|
|
|
|
2014-05-14 01:37:35 -06:00
|
|
|
static const struct ak4642_drvdata ak4642_drvdata = {
|
|
|
|
.regmap_config = &ak4642_regmap,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ak4642_drvdata ak4643_drvdata = {
|
2015-06-30 10:56:36 -06:00
|
|
|
.regmap_config = &ak4643_regmap,
|
2014-05-14 01:37:35 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static const struct ak4642_drvdata ak4648_drvdata = {
|
|
|
|
.regmap_config = &ak4648_regmap,
|
2014-05-14 01:37:36 -06:00
|
|
|
.extended_frequencies = 1,
|
2014-05-14 01:37:35 -06:00
|
|
|
};
|
|
|
|
|
2015-09-10 00:40:19 -06:00
|
|
|
#ifdef CONFIG_COMMON_CLK
|
|
|
|
static struct clk *ak4642_of_parse_mcko(struct device *dev)
|
|
|
|
{
|
|
|
|
struct device_node *np = dev->of_node;
|
|
|
|
struct clk *clk;
|
|
|
|
const char *clk_name = np->name;
|
|
|
|
const char *parent_clk_name = NULL;
|
|
|
|
u32 rate;
|
|
|
|
|
|
|
|
if (of_property_read_u32(np, "clock-frequency", &rate))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (of_property_read_bool(np, "clocks"))
|
|
|
|
parent_clk_name = of_clk_get_parent_name(np, 0);
|
|
|
|
|
|
|
|
of_property_read_string(np, "clock-output-names", &clk_name);
|
|
|
|
|
2016-04-19 19:05:04 -06:00
|
|
|
clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);
|
2015-09-10 00:40:19 -06:00
|
|
|
if (!IS_ERR(clk))
|
|
|
|
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
|
|
|
|
|
|
|
return clk;
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
#define ak4642_of_parse_mcko(d) 0
|
|
|
|
#endif
|
|
|
|
|
2014-07-28 00:11:04 -06:00
|
|
|
static const struct of_device_id ak4642_of_match[];
|
2012-12-07 07:26:37 -07:00
|
|
|
static int ak4642_i2c_probe(struct i2c_client *i2c,
|
|
|
|
const struct i2c_device_id *id)
|
2009-08-20 19:23:41 -06:00
|
|
|
{
|
2015-09-10 00:39:59 -06:00
|
|
|
struct device *dev = &i2c->dev;
|
|
|
|
struct device_node *np = dev->of_node;
|
2014-05-14 01:37:35 -06:00
|
|
|
const struct ak4642_drvdata *drvdata = NULL;
|
2013-11-28 11:03:49 -07:00
|
|
|
struct regmap *regmap;
|
2014-05-14 01:37:35 -06:00
|
|
|
struct ak4642_priv *priv;
|
2015-09-10 00:40:19 -06:00
|
|
|
struct clk *mcko = NULL;
|
2013-01-10 01:29:11 -07:00
|
|
|
|
|
|
|
if (np) {
|
|
|
|
const struct of_device_id *of_id;
|
|
|
|
|
2015-09-10 00:40:19 -06:00
|
|
|
mcko = ak4642_of_parse_mcko(dev);
|
|
|
|
if (IS_ERR(mcko))
|
|
|
|
mcko = NULL;
|
|
|
|
|
2015-09-10 00:39:59 -06:00
|
|
|
of_id = of_match_device(ak4642_of_match, dev);
|
2013-01-10 01:29:11 -07:00
|
|
|
if (of_id)
|
2014-05-14 01:37:35 -06:00
|
|
|
drvdata = of_id->data;
|
2013-01-10 01:29:11 -07:00
|
|
|
} else {
|
2014-05-14 01:37:35 -06:00
|
|
|
drvdata = (const struct ak4642_drvdata *)id->driver_data;
|
2013-01-10 01:29:11 -07:00
|
|
|
}
|
|
|
|
|
2014-05-14 01:37:35 -06:00
|
|
|
if (!drvdata) {
|
2015-09-10 00:39:59 -06:00
|
|
|
dev_err(dev, "Unknown device type\n");
|
2013-01-10 01:29:11 -07:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2015-09-10 00:39:59 -06:00
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
2014-05-14 01:37:35 -06:00
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
priv->drvdata = drvdata;
|
2015-09-10 00:40:19 -06:00
|
|
|
priv->mcko = mcko;
|
2014-05-14 01:37:35 -06:00
|
|
|
|
|
|
|
i2c_set_clientdata(i2c, priv);
|
|
|
|
|
|
|
|
regmap = devm_regmap_init_i2c(i2c, drvdata->regmap_config);
|
2013-11-28 11:03:49 -07:00
|
|
|
if (IS_ERR(regmap))
|
|
|
|
return PTR_ERR(regmap);
|
|
|
|
|
2015-09-10 00:39:59 -06:00
|
|
|
return snd_soc_register_codec(dev,
|
2013-11-28 11:03:49 -07:00
|
|
|
&soc_codec_dev_ak4642, &ak4642_dai, 1);
|
2009-08-20 19:23:41 -06:00
|
|
|
}
|
|
|
|
|
2012-12-07 07:26:37 -07:00
|
|
|
static int ak4642_i2c_remove(struct i2c_client *client)
|
2009-08-20 19:23:41 -06:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
snd_soc_unregister_codec(&client->dev);
|
2009-08-20 19:23:41 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-07-28 00:11:04 -06:00
|
|
|
static const struct of_device_id ak4642_of_match[] = {
|
2014-05-14 01:37:35 -06:00
|
|
|
{ .compatible = "asahi-kasei,ak4642", .data = &ak4642_drvdata},
|
|
|
|
{ .compatible = "asahi-kasei,ak4643", .data = &ak4643_drvdata},
|
|
|
|
{ .compatible = "asahi-kasei,ak4648", .data = &ak4648_drvdata},
|
2013-01-10 01:29:11 -07:00
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, ak4642_of_match);
|
|
|
|
|
2009-08-20 19:23:41 -06:00
|
|
|
static const struct i2c_device_id ak4642_i2c_id[] = {
|
2014-05-14 01:37:35 -06:00
|
|
|
{ "ak4642", (kernel_ulong_t)&ak4642_drvdata },
|
|
|
|
{ "ak4643", (kernel_ulong_t)&ak4643_drvdata },
|
|
|
|
{ "ak4648", (kernel_ulong_t)&ak4648_drvdata },
|
2009-08-20 19:23:41 -06:00
|
|
|
{ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
|
|
|
|
|
|
|
|
static struct i2c_driver ak4642_i2c_driver = {
|
|
|
|
.driver = {
|
2010-03-17 14:15:21 -06:00
|
|
|
.name = "ak4642-codec",
|
2013-01-10 01:29:11 -07:00
|
|
|
.of_match_table = ak4642_of_match,
|
2009-08-20 19:23:41 -06:00
|
|
|
},
|
2010-09-15 22:06:40 -06:00
|
|
|
.probe = ak4642_i2c_probe,
|
2012-12-07 07:26:37 -07:00
|
|
|
.remove = ak4642_i2c_remove,
|
2010-09-15 22:06:40 -06:00
|
|
|
.id_table = ak4642_i2c_id,
|
2009-08-20 19:23:41 -06:00
|
|
|
};
|
|
|
|
|
2013-11-28 10:24:55 -07:00
|
|
|
module_i2c_driver(ak4642_i2c_driver);
|
2009-08-20 19:23:41 -06:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Soc AK4642 driver");
|
|
|
|
MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
|
|
|
|
MODULE_LICENSE("GPL");
|