2013-06-18 09:29:34 -06:00
|
|
|
/*
|
|
|
|
* Samsung's Exynos5 SoC series common device tree source
|
|
|
|
*
|
|
|
|
* Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
|
|
|
|
* http://www.samsung.com
|
|
|
|
*
|
|
|
|
* Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
|
|
|
|
* SoCs from Exynos5 series can include this file and provide values for SoCs
|
|
|
|
* specfic bindings.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
|
|
|
|
2016-09-16 15:41:59 -06:00
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
2016-09-16 13:42:47 -06:00
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
2016-02-16 08:25:48 -07:00
|
|
|
#include "exynos-syscon-restart.dtsi"
|
2013-06-18 09:29:34 -06:00
|
|
|
|
|
|
|
/ {
|
|
|
|
interrupt-parent = <&gic>;
|
2016-09-01 03:06:53 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
2013-06-18 09:29:34 -06:00
|
|
|
|
2014-06-26 05:24:35 -06:00
|
|
|
aliases {
|
2016-05-03 06:51:25 -06:00
|
|
|
i2c0 = &i2c_0;
|
|
|
|
i2c1 = &i2c_1;
|
|
|
|
i2c2 = &i2c_2;
|
|
|
|
i2c3 = &i2c_3;
|
2014-06-26 05:24:35 -06:00
|
|
|
serial0 = &serial_0;
|
|
|
|
serial1 = &serial_1;
|
|
|
|
serial2 = &serial_2;
|
|
|
|
serial3 = &serial_3;
|
|
|
|
};
|
|
|
|
|
2016-05-03 10:53:04 -06:00
|
|
|
soc: soc {
|
|
|
|
compatible = "simple-bus";
|
2013-08-14 02:15:00 -06:00
|
|
|
#address-cells = <1>;
|
2016-05-03 10:53:04 -06:00
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
chipid@10000000 {
|
|
|
|
compatible = "samsung,exynos4210-chipid";
|
|
|
|
reg = <0x10000000 0x100>;
|
|
|
|
};
|
|
|
|
|
|
|
|
sromc: memory-controller@12250000 {
|
|
|
|
compatible = "samsung,exynos4210-srom";
|
|
|
|
reg = <0x12250000 0x14>;
|
|
|
|
};
|
|
|
|
|
|
|
|
combiner: interrupt-controller@10440000 {
|
|
|
|
compatible = "samsung,exynos4210-combiner";
|
|
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
|
|
samsung,combiner-nr = <32>;
|
|
|
|
reg = <0x10440000 0x1000>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 12 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 15 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 20 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 28 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 29 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 30 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 31 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
gic: interrupt-controller@10481000 {
|
2017-01-18 02:27:28 -07:00
|
|
|
compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
|
2016-05-03 10:53:04 -06:00
|
|
|
#interrupt-cells = <3>;
|
|
|
|
interrupt-controller;
|
|
|
|
reg = <0x10481000 0x1000>,
|
2017-01-18 02:27:28 -07:00
|
|
|
<0x10482000 0x2000>,
|
2016-05-03 10:53:04 -06:00
|
|
|
<0x10484000 0x2000>,
|
|
|
|
<0x10486000 0x2000>;
|
2016-09-16 15:41:59 -06:00
|
|
|
interrupts = <GIC_PPI 9
|
|
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
sysreg_system_controller: syscon@10050000 {
|
|
|
|
compatible = "samsung,exynos5-sysreg", "syscon";
|
|
|
|
reg = <0x10050000 0x5000>;
|
|
|
|
};
|
|
|
|
|
|
|
|
serial_0: serial@12C00000 {
|
|
|
|
compatible = "samsung,exynos4210-uart";
|
|
|
|
reg = <0x12C00000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
serial_1: serial@12C10000 {
|
|
|
|
compatible = "samsung,exynos4210-uart";
|
|
|
|
reg = <0x12C10000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
serial_2: serial@12C20000 {
|
|
|
|
compatible = "samsung,exynos4210-uart";
|
|
|
|
reg = <0x12C20000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
serial_3: serial@12C30000 {
|
|
|
|
compatible = "samsung,exynos4210-uart";
|
|
|
|
reg = <0x12C30000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
i2c_0: i2c@12C60000 {
|
|
|
|
compatible = "samsung,s3c2440-i2c";
|
|
|
|
reg = <0x12C60000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c_1: i2c@12C70000 {
|
|
|
|
compatible = "samsung,s3c2440-i2c";
|
|
|
|
reg = <0x12C70000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c_2: i2c@12C80000 {
|
|
|
|
compatible = "samsung,s3c2440-i2c";
|
|
|
|
reg = <0x12C80000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
i2c_3: i2c@12C90000 {
|
|
|
|
compatible = "samsung,s3c2440-i2c";
|
|
|
|
reg = <0x12C90000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
samsung,sysreg-phandle = <&sysreg_system_controller>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
pwm: pwm@12DD0000 {
|
|
|
|
compatible = "samsung,exynos4210-pwm";
|
|
|
|
reg = <0x12DD0000 0x100>;
|
|
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
|
|
|
|
#pwm-cells = <3>;
|
|
|
|
};
|
|
|
|
|
|
|
|
rtc: rtc@101E0000 {
|
|
|
|
compatible = "samsung,s3c6410-rtc";
|
|
|
|
reg = <0x101E0000 0x100>;
|
2016-09-16 13:42:47 -06:00
|
|
|
interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
|
<0 44 IRQ_TYPE_LEVEL_HIGH>;
|
2016-05-03 10:53:04 -06:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
fimd: fimd@14400000 {
|
|
|
|
compatible = "samsung,exynos5250-fimd";
|
|
|
|
interrupt-parent = <&combiner>;
|
|
|
|
reg = <0x14400000 0x40000>;
|
|
|
|
interrupt-names = "fifo", "vsync", "lcd_sys";
|
|
|
|
interrupts = <18 4>, <18 5>, <18 6>;
|
|
|
|
samsung,sysreg = <&sysreg_system_controller>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
dp: dp-controller@145B0000 {
|
|
|
|
compatible = "samsung,exynos5-dp";
|
|
|
|
reg = <0x145B0000 0x1000>;
|
|
|
|
interrupts = <10 3>;
|
|
|
|
interrupt-parent = <&combiner>;
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2013-08-14 02:15:00 -06:00
|
|
|
};
|
2013-06-18 09:29:34 -06:00
|
|
|
};
|