2013-07-25 18:36:16 -06:00
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/*
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* Device Tree Source for the Marzen board
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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2013-11-09 05:23:53 -07:00
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#include "r8a7779.dtsi"
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2014-05-15 05:31:58 -06:00
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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2013-07-25 18:36:16 -06:00
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/ {
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model = "marzen";
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compatible = "renesas,marzen", "renesas,r8a7779";
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2014-05-15 05:39:32 -06:00
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aliases {
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2015-08-06 20:45:33 -06:00
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serial0 = &scif2;
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serial1 = &scif4;
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2014-05-15 05:39:32 -06:00
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};
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2013-07-25 18:36:16 -06:00
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chosen {
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2015-08-06 20:45:33 -06:00
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bootargs = "ignore_loglevel root=/dev/nfs ip=on";
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2016-06-14 08:15:22 -06:00
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stdout-path = "serial0:115200n8";
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2013-07-25 18:36:16 -06:00
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};
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2016-05-20 01:10:10 -06:00
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memory@60000000 {
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2013-07-25 18:36:16 -06:00
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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2014-05-15 05:31:58 -06:00
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2016-05-20 01:10:10 -06:00
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fixedregulator3v3: regulator-3v3 {
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2014-05-15 05:31:58 -06:00
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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2015-04-27 06:55:34 -06:00
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ethernet@18000000 {
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2014-05-15 05:31:58 -06:00
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compatible = "smsc,lan9220", "smsc,lan9115";
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reg = <0x18000000 0x100>;
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2015-04-27 06:55:34 -06:00
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pinctrl-0 = <ðernet_pins>;
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2014-05-15 05:31:58 -06:00
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pinctrl-names = "default";
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phy-mode = "mii";
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interrupt-parent = <&irqpin0>;
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interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
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smsc,irq-push-pull;
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reg-io-width = <4>;
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vddvario-supply = <&fixedregulator3v3>;
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vdd33a-supply = <&fixedregulator3v3>;
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};
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leds {
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compatible = "gpio-leds";
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led2 {
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gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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};
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led3 {
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gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
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};
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led4 {
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gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
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};
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};
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2014-08-27 03:11:45 -06:00
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vga-encoder {
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compatible = "adi,adv7123";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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vga_enc_in: endpoint {
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remote-endpoint = <&du_out_rgb0>;
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};
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};
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port@1 {
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reg = <1>;
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vga_enc_out: endpoint {
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remote-endpoint = <&vga_in>;
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};
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};
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};
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};
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vga {
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compatible = "vga-connector";
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port {
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vga_in: endpoint {
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remote-endpoint = <&vga_enc_out>;
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};
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};
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};
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lvds-encoder {
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compatible = "thine,thc63lvdm83d";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds_enc_in: endpoint {
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remote-endpoint = <&du_out_rgb1>;
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};
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};
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port@1 {
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reg = <1>;
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lvds_connector: endpoint {
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};
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};
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};
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};
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2015-02-26 02:21:21 -07:00
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x3_clk: x3-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <65000000>;
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};
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2014-08-27 03:11:45 -06:00
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};
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&du {
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pinctrl-0 = <&du_pins>;
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pinctrl-names = "default";
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status = "okay";
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2015-02-26 02:21:21 -07:00
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clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
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clock-names = "du", "dclkin.0";
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2014-08-27 03:11:45 -06:00
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ports {
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port@0 {
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endpoint {
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remote-endpoint = <&vga_enc_in>;
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};
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};
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port@1 {
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endpoint {
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remote-endpoint = <&lvds_enc_in>;
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};
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};
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};
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2014-05-15 05:31:58 -06:00
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};
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&irqpin0 {
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status = "okay";
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};
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2014-05-15 05:31:59 -06:00
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&extal_clk {
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clock-frequency = <31250000>;
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};
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2014-07-09 07:12:43 -06:00
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&tmu0 {
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status = "okay";
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};
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2014-05-15 05:31:58 -06:00
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&pfc {
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2016-01-29 03:17:23 -07:00
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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2014-08-27 03:11:45 -06:00
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du_pins: du {
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du0 {
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2016-10-21 06:27:43 -06:00
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groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0", "du0_clk_in";
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2016-03-17 16:54:24 -06:00
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function = "du0";
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2014-08-27 03:11:45 -06:00
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};
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du1 {
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2016-03-17 16:54:24 -06:00
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groups = "du1_rgb666", "du1_sync_1", "du1_clk_out";
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function = "du1";
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2014-08-27 03:11:45 -06:00
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};
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};
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2016-01-29 03:17:23 -07:00
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scif_clk_pins: scif_clk {
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2016-03-17 16:54:24 -06:00
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groups = "scif_clk_b";
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function = "scif_clk";
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2016-01-29 03:17:23 -07:00
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};
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2015-04-27 06:55:34 -06:00
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ethernet_pins: ethernet {
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2014-05-15 05:31:58 -06:00
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intc {
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2016-03-17 16:54:24 -06:00
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groups = "intc_irq1_b";
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function = "intc";
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2014-05-15 05:31:58 -06:00
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};
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lbsc {
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2016-03-17 16:54:24 -06:00
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groups = "lbsc_ex_cs0";
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function = "lbsc";
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2014-05-15 05:31:58 -06:00
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};
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};
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2016-06-10 07:00:51 -06:00
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scif2_pins: scif2 {
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2016-03-17 16:54:24 -06:00
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groups = "scif2_data_c";
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function = "scif2";
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2014-05-15 05:31:58 -06:00
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};
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2016-06-10 07:00:51 -06:00
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scif4_pins: scif4 {
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2016-03-17 16:54:24 -06:00
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groups = "scif4_data";
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function = "scif4";
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2014-05-15 05:31:58 -06:00
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};
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sdhi0_pins: sd0 {
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2016-03-17 16:54:24 -06:00
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groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";
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function = "sdhi0";
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2014-05-15 05:31:58 -06:00
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};
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hspi0_pins: hspi0 {
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2016-03-17 16:54:24 -06:00
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groups = "hspi0";
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function = "hspi0";
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2014-05-15 05:31:58 -06:00
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};
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};
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2017-01-16 09:56:53 -07:00
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&sata {
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status = "okay";
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};
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2014-05-15 05:39:32 -06:00
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&scif2 {
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2014-07-07 00:47:37 -06:00
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pinctrl-0 = <&scif2_pins>;
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pinctrl-names = "default";
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2014-05-15 05:39:32 -06:00
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2014-07-07 00:47:37 -06:00
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status = "okay";
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2014-05-15 05:39:32 -06:00
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};
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&scif4 {
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2014-07-07 00:47:37 -06:00
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pinctrl-0 = <&scif4_pins>;
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pinctrl-names = "default";
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2014-05-15 05:39:32 -06:00
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2014-07-07 00:47:37 -06:00
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status = "okay";
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2014-05-15 05:39:32 -06:00
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};
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2016-01-29 03:17:23 -07:00
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&scif_clk {
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clock-frequency = <14745600>;
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status = "okay";
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};
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2014-05-15 05:31:58 -06:00
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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vmmc-supply = <&fixedregulator3v3>;
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bus-width = <4>;
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status = "okay";
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};
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&hspi0 {
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pinctrl-0 = <&hspi0_pins>;
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pinctrl-names = "default";
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status = "okay";
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2013-07-25 18:36:16 -06:00
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};
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