2012-06-19 09:31:53 -06:00
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/*
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* Platform data for Arizona devices
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*
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* Copyright 2012 Wolfson Microelectronics. PLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ARIZONA_PDATA_H
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#define _ARIZONA_PDATA_H
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#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
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#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
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#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
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#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
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#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
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#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
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#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
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#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
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#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
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#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
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#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
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#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
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#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
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#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
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#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
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#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
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#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
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#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
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#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
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#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
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#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
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#define ARIZONA_MAX_GPIO 5
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#define ARIZONA_32KZ_MCLK1 1
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#define ARIZONA_32KZ_MCLK2 2
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#define ARIZONA_32KZ_NONE 3
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2012-07-10 05:37:58 -06:00
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#define ARIZONA_MAX_INPUT 4
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2012-06-19 09:31:53 -06:00
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#define ARIZONA_DMIC_MICVDD 0
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#define ARIZONA_DMIC_MICBIAS1 1
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#define ARIZONA_DMIC_MICBIAS2 2
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#define ARIZONA_DMIC_MICBIAS3 3
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2013-01-28 09:47:37 -07:00
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#define ARIZONA_MAX_MICBIAS 3
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2012-06-19 09:31:53 -06:00
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#define ARIZONA_INMODE_DIFF 0
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#define ARIZONA_INMODE_SE 1
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#define ARIZONA_INMODE_DMIC 2
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2012-07-10 05:37:58 -06:00
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#define ARIZONA_MAX_OUTPUT 6
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2012-06-19 09:31:53 -06:00
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2013-01-17 00:35:14 -07:00
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#define ARIZONA_MAX_AIF 3
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2012-11-26 14:17:21 -07:00
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#define ARIZONA_HAP_ACT_ERM 0
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#define ARIZONA_HAP_ACT_LRA 2
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2012-07-09 12:33:14 -06:00
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#define ARIZONA_MAX_PDM_SPK 2
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2012-06-19 09:31:53 -06:00
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struct regulator_init_data;
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2013-01-28 09:47:37 -07:00
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struct arizona_micbias {
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int mV; /** Regulated voltage */
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unsigned int ext_cap:1; /** External capacitor fitted */
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unsigned int discharge:1; /** Actively discharge */
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2013-05-21 07:56:58 -06:00
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unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
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2013-01-29 03:44:41 -07:00
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unsigned int bypass:1; /** Use bypass mode */
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2013-01-28 09:47:37 -07:00
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};
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2012-06-19 09:31:53 -06:00
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struct arizona_micd_config {
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unsigned int src;
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unsigned int bias;
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bool gpio;
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};
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2013-04-01 15:03:06 -06:00
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struct arizona_micd_range {
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int max; /** Ohms */
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int key; /** Key to report to input layer */
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};
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2012-06-19 09:31:53 -06:00
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struct arizona_pdata {
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int reset; /** GPIO controlling /RESET, if any */
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int ldoena; /** GPIO controlling LODENA, if any */
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/** Regulator configuration for MICVDD */
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struct regulator_init_data *micvdd;
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/** Regulator configuration for LDO1 */
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struct regulator_init_data *ldo1;
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/** If a direct 32kHz clock is provided on an MCLK specify it here */
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int clk32k_src;
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2013-03-22 05:59:33 -06:00
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/** Mode for primary IRQ (defaults to active low) */
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unsigned int irq_flags;
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2012-06-19 09:31:53 -06:00
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/* Base GPIO */
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int gpio_base;
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/** Pin state for GPIO pins */
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int gpio_defaults[ARIZONA_MAX_GPIO];
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2013-01-17 00:35:14 -07:00
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/**
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* Maximum number of channels clocks will be generated for,
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* useful for systems where and I2S bus with multiple data
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* lines is mastered.
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*/
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int max_channels_clocked[ARIZONA_MAX_AIF];
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2013-01-10 16:55:39 -07:00
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/** GPIO5 is used for jack detection */
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bool jd_gpio5;
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2013-04-01 12:03:52 -06:00
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/** Internal pull on GPIO5 is disabled when used for jack detection */
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bool jd_gpio5_nopull;
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2013-01-10 16:55:51 -07:00
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/** Use the headphone detect circuit to identify the accessory */
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bool hpdet_acc_id;
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2013-02-25 16:42:31 -07:00
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/** Check for line output with HPDET method */
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bool hpdet_acc_id_line;
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2013-01-10 16:55:54 -07:00
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/** GPIO used for mic isolation with HPDET */
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int hpdet_id_gpio;
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2013-04-01 12:21:48 -06:00
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/** Extra debounce timeout used during initial mic detection (ms) */
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int micd_detect_debounce;
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2012-06-19 09:31:53 -06:00
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/** GPIO for mic detection polarity */
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int micd_pol_gpio;
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2013-01-10 16:55:24 -07:00
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/** Mic detect ramp rate */
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int micd_bias_start_time;
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2013-01-21 01:36:33 -07:00
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/** Mic detect sample rate */
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int micd_rate;
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/** Mic detect debounce level */
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int micd_dbtime;
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2013-04-01 12:25:55 -06:00
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/** Mic detect timeout (ms) */
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int micd_timeout;
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2013-01-10 12:38:43 -07:00
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/** Force MICBIAS on for mic detect */
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bool micd_force_micbias;
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2013-04-01 15:03:06 -06:00
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/** Mic detect level parameters */
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const struct arizona_micd_range *micd_ranges;
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int num_micd_ranges;
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2012-06-19 09:31:53 -06:00
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/** Headset polarity configurations */
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struct arizona_micd_config *micd_configs;
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int num_micd_configs;
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/** Reference voltage for DMIC inputs */
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int dmic_ref[ARIZONA_MAX_INPUT];
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2013-01-28 09:47:37 -07:00
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/** MICBIAS configurations */
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struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
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2012-06-19 09:31:53 -06:00
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/** Mode of input structures */
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int inmode[ARIZONA_MAX_INPUT];
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/** Mode for outputs */
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bool out_mono[ARIZONA_MAX_OUTPUT];
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/** PDM speaker mute setting */
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unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
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/** PDM speaker format */
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unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
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2012-11-26 14:17:21 -07:00
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/** Haptic actuator type */
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unsigned int hap_act;
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2013-03-24 17:05:58 -06:00
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/** GPIO for primary IRQ (used for edge triggered emulation) */
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int irq_gpio;
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2012-06-19 09:31:53 -06:00
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};
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#endif
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