ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address. Take the opportunity to use the node label instead of the full name. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This commit is contained in:
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1fc2129553
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007d05d898
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@ -73,28 +73,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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/* First mini-PCIe port */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Second mini-PCIe port */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Renesas uPD720202 USB 3.0 controller */
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pcie@3,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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};
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internal-regs {
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/* UART0 */
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serial@12000 {
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@ -153,6 +131,28 @@
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};
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};
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&pciec {
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status = "okay";
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/* First mini-PCIe port */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Second mini-PCIe port */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Renesas uPD720202 USB 3.0 controller */
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pcie@3,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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};
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&pinctrl {
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pinctrl-0 = <&phy_int_pin>;
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pinctrl-names = "default";
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@ -108,39 +108,6 @@
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* All 6 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 0, Lane 2 */
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status = "okay";
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};
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pcie@4,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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@ -248,6 +215,39 @@
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};
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};
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&pciec {
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status = "okay";
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/*
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* All 6 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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pcie@3,0 {
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/* Port 0, Lane 2 */
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status = "okay";
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};
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pcie@4,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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@ -127,27 +127,6 @@
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};
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};
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pcie-controller {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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@ -233,6 +212,27 @@
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};
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};
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&pciec {
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status = "okay";
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/*
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* The 3 slots are physically present as
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* standard PCIe slots on the board.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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pcie@9,0 {
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/* Port 2, Lane 0 */
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status = "okay";
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};
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pcie@10,0 {
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/* Port 3, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <16>;
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@ -68,22 +68,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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/* Quad port sata: Marvell 88SX7042 */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* USB 3.0 xHCI controller: NEC D720200F1 */
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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@ -285,6 +269,21 @@
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gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
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};
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};
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&pciec {
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status = "okay";
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/* Quad port sata: Marvell 88SX7042 */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* USB 3.0 xHCI controller: NEC D720200F1 */
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 { /* Marvell 88E1318 */
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@ -73,28 +73,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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/* Etron EJ168 USB 3.0 controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* First mini-PCIe port */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Second mini-PCIe port */
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pcie@3,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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};
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internal-regs {
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rtc@10300 {
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@ -369,6 +347,28 @@
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};
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};
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&pciec {
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status = "okay";
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/* Etron EJ168 USB 3.0 controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* First mini-PCIe port */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Second mini-PCIe port */
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pcie@3,0 {
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/* Port 0, Lane 3 */
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status = "okay";
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};
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};
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&pinctrl {
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keys_pin: keys-pin {
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@ -71,15 +71,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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serial@12000 {
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status = "okay";
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@ -114,3 +105,12 @@
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};
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};
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};
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&pciec {
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status = "okay";
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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@ -86,7 +86,7 @@
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* configured as x4 or quad x1 lanes. One unit is
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* x1 only.
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*/
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pciec: pcie-controller {
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pciec: pcie-controller@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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@ -87,7 +87,7 @@
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* configured as x4 or quad x1 lanes. One unit is
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* x4 only.
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*/
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pciec: pcie-controller {
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pciec: pcie-controller@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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@ -104,7 +104,7 @@
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* configured as x4 or quad x1 lanes. Two units are
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* x4/x1.
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*/
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pciec: pcie-controller {
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pciec: pcie-controller@82000000 {
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compatible = "marvell,armada-xp-pcie";
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status = "disabled";
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device_type = "pci";
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@ -67,28 +67,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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/* Connected to first Marvell 88SE9170 SATA controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Connected to second Marvell 88SE9170 SATA controller */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Connected to Fresco Logic FL1009 USB 3.0 controller */
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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/* RTC is provided by Intersil ISL12057 I2C RTC chip */
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@ -290,6 +268,28 @@
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};
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};
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&pciec {
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status = "okay";
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/* Connected to first Marvell 88SE9170 SATA controller */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/* Connected to second Marvell 88SE9170 SATA controller */
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pcie@2,0 {
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/* Port 0, Lane 1 */
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status = "okay";
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};
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/* Connected to Fresco Logic FL1009 USB 3.0 controller */
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 { /* Marvell 88E1318 */
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reg = <0>;
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@ -98,15 +98,6 @@
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};
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};
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pcie-controller {
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status = "okay";
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/* Internal mini-PCIe connector */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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rtc@10300 {
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/* No crystal connected to the internal RTC */
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@ -222,6 +213,15 @@
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};
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};
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&pciec {
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status = "okay";
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/* Internal mini-PCIe connector */
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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@ -81,28 +81,6 @@
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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/*
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* Connected to Marvell 88SX7042 SATA-II controller
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* handling the four disks.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/*
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* Connected to EtronTech EJ168A XHCI controller
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* providing the two rear USB 3.0 ports.
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*/
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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/* RTC is provided by Seiko S-35390A below */
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@ -230,6 +208,29 @@
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};
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};
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&pciec {
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status = "okay";
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/*
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* Connected to Marvell 88SX7042 SATA-II controller
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* handling the four disks.
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*/
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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/*
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* Connected to EtronTech EJ168A XHCI controller
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* providing the two rear USB 3.0 ports.
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*/
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pcie@5,0 {
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/* Port 1, Lane 0 */
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status = "okay";
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};
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};
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&mdio {
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phy0: ethernet-phy@0 { /* Marvell 88E1512 */
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reg = <0>;
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