Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 page table isolation fixes from Thomas Gleixner: "A couple of urgent fixes for PTI: - Fix a PTE mismatch between user and kernel visible mapping of the cpu entry area (differs vs. the GLB bit) and causes a TLB mismatch MCE on older AMD K8 machines - Fix the misplaced CR3 switch in the SYSCALL compat entry code which causes access to unmapped kernel memory resulting in double faults. - Fix the section mismatch of the cpu_tss_rw percpu storage caused by using a different mechanism for declaration and definition. - Two fixes for dumpstack which help to decode entry stack issues better - Enable PTI by default in Kconfig. We should have done that earlier, but it slipped through the cracks. - Exclude AMD from the PTI enforcement. Not necessarily a fix, but if AMD is so confident that they are not affected, then we should not burden users with the overhead" * 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/process: Define cpu_tss_rw in same section as declaration x86/pti: Switch to kernel CR3 at early in entry_SYSCALL_compat() x86/dumpstack: Print registers for first stack frame x86/dumpstack: Fix partial register dumps x86/pti: Make sure the user/kernel PTEs match x86/cpu, x86/pti: Do not enable PTI on AMD processors x86/pti: Enable PTI by default
This commit is contained in:
commit
00a5ae218d
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@ -190,8 +190,13 @@ ENTRY(entry_SYSCALL_compat)
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/* Interrupts are off on entry. */
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swapgs
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/* Stash user ESP and switch to the kernel stack. */
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/* Stash user ESP */
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movl %esp, %r8d
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/* Use %rsp as scratch reg. User ESP is stashed in r8 */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
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/* Switch to the kernel stack */
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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/* Construct struct pt_regs on stack */
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@ -219,12 +224,6 @@ GLOBAL(entry_SYSCALL_compat_after_hwframe)
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pushq $0 /* pt_regs->r14 = 0 */
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pushq $0 /* pt_regs->r15 = 0 */
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/*
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* We just saved %rdi so it is safe to clobber. It is not
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* preserved during the C calls inside TRACE_IRQS_OFF anyway.
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*/
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
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/*
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* User mode is traced as though IRQs are on, and SYSENTER
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* turned them off.
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@ -56,18 +56,27 @@ void unwind_start(struct unwind_state *state, struct task_struct *task,
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#if defined(CONFIG_UNWINDER_ORC) || defined(CONFIG_UNWINDER_FRAME_POINTER)
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/*
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* WARNING: The entire pt_regs may not be safe to dereference. In some cases,
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* only the iret frame registers are accessible. Use with caution!
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* If 'partial' returns true, only the iret frame registers are valid.
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*/
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static inline struct pt_regs *unwind_get_entry_regs(struct unwind_state *state)
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static inline struct pt_regs *unwind_get_entry_regs(struct unwind_state *state,
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bool *partial)
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{
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if (unwind_done(state))
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return NULL;
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if (partial) {
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#ifdef CONFIG_UNWINDER_ORC
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*partial = !state->full_regs;
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#else
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*partial = false;
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#endif
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}
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return state->regs;
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}
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#else
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static inline struct pt_regs *unwind_get_entry_regs(struct unwind_state *state)
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static inline struct pt_regs *unwind_get_entry_regs(struct unwind_state *state,
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bool *partial)
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{
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return NULL;
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}
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@ -923,8 +923,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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setup_force_cpu_cap(X86_FEATURE_ALWAYS);
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/* Assume for now that ALL x86 CPUs are insecure */
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setup_force_cpu_bug(X86_BUG_CPU_INSECURE);
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if (c->x86_vendor != X86_VENDOR_AMD)
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setup_force_cpu_bug(X86_BUG_CPU_INSECURE);
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fpu__init_system(c);
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@ -76,12 +76,23 @@ void show_iret_regs(struct pt_regs *regs)
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regs->sp, regs->flags);
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}
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static void show_regs_safe(struct stack_info *info, struct pt_regs *regs)
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static void show_regs_if_on_stack(struct stack_info *info, struct pt_regs *regs,
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bool partial)
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{
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if (on_stack(info, regs, sizeof(*regs)))
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/*
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* These on_stack() checks aren't strictly necessary: the unwind code
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* has already validated the 'regs' pointer. The checks are done for
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* ordering reasons: if the registers are on the next stack, we don't
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* want to print them out yet. Otherwise they'll be shown as part of
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* the wrong stack. Later, when show_trace_log_lvl() switches to the
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* next stack, this function will be called again with the same regs so
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* they can be printed in the right context.
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*/
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if (!partial && on_stack(info, regs, sizeof(*regs))) {
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__show_regs(regs, 0);
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else if (on_stack(info, (void *)regs + IRET_FRAME_OFFSET,
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IRET_FRAME_SIZE)) {
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} else if (partial && on_stack(info, (void *)regs + IRET_FRAME_OFFSET,
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IRET_FRAME_SIZE)) {
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/*
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* When an interrupt or exception occurs in entry code, the
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* full pt_regs might not have been saved yet. In that case
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@ -98,11 +109,13 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
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struct stack_info stack_info = {0};
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unsigned long visit_mask = 0;
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int graph_idx = 0;
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bool partial;
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printk("%sCall Trace:\n", log_lvl);
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unwind_start(&state, task, regs, stack);
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stack = stack ? : get_stack_pointer(task, regs);
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regs = unwind_get_entry_regs(&state, &partial);
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/*
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* Iterate through the stacks, starting with the current stack pointer.
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@ -120,7 +133,7 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
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* - hardirq stack
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* - entry stack
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*/
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for (regs = NULL; stack; stack = PTR_ALIGN(stack_info.next_sp, sizeof(long))) {
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for ( ; stack; stack = PTR_ALIGN(stack_info.next_sp, sizeof(long))) {
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const char *stack_name;
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if (get_stack_info(stack, task, &stack_info, &visit_mask)) {
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@ -140,7 +153,7 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
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printk("%s <%s>\n", log_lvl, stack_name);
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if (regs)
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show_regs_safe(&stack_info, regs);
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show_regs_if_on_stack(&stack_info, regs, partial);
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/*
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* Scan the stack, printing any text addresses we find. At the
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@ -164,7 +177,7 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
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/*
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* Don't print regs->ip again if it was already printed
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* by show_regs_safe() below.
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* by show_regs_if_on_stack().
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*/
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if (regs && stack == ®s->ip)
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goto next;
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@ -199,9 +212,9 @@ next:
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unwind_next_frame(&state);
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/* if the frame has entry regs, print them */
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regs = unwind_get_entry_regs(&state);
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regs = unwind_get_entry_regs(&state, &partial);
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if (regs)
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show_regs_safe(&stack_info, regs);
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show_regs_if_on_stack(&stack_info, regs, partial);
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}
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if (stack_name)
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@ -47,7 +47,7 @@
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss_rw) = {
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__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
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.x86_tss = {
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/*
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* .sp0 is only used when entering ring 0 from a lower
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@ -102,7 +102,7 @@ __save_stack_trace_reliable(struct stack_trace *trace,
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for (unwind_start(&state, task, NULL, NULL); !unwind_done(&state);
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unwind_next_frame(&state)) {
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regs = unwind_get_entry_regs(&state);
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regs = unwind_get_entry_regs(&state, NULL);
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if (regs) {
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/*
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* Kernel mode registers on the stack indicate an
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@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void)
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static void __init pti_clone_entry_text(void)
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{
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pti_clone_pmds((unsigned long) __entry_text_start,
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(unsigned long) __irqentry_text_end, _PAGE_RW);
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(unsigned long) __irqentry_text_end,
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_PAGE_RW | _PAGE_GLOBAL);
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}
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/*
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@ -56,6 +56,7 @@ config SECURITY_NETWORK
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config PAGE_TABLE_ISOLATION
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bool "Remove the kernel mapping in user mode"
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default y
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depends on X86_64 && !UML
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help
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This feature reduces the number of hardware side channels by
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