ASoC: rsnd: SRC TIMSEL support for Capture
SRC has Sync/Async mode, and it can't use Sync mode when Capture with CMD. In Async mode, it needs to care about in/out SRC rate for settings, but current driver supporting Playback case only. This patch supports Capture case. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>steinar/wifi_calib_4_9_kernel
Kuninori Morimoto
Mark Brown
parent
cbf1494fbc
commit
0102eed57c
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@ -90,6 +90,108 @@ static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
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return (0x6 + ws) << 8;
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}
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static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int target_rate,
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unsigned int *target_val,
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unsigned int *target_en)
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, step;
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unsigned int val, en;
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unsigned int min, diff;
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unsigned int sel_rate[] = {
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clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
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adg->rbga_rate_for_441khz, /* 0011: RBGA */
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adg->rbgb_rate_for_48khz, /* 0100: RBGB */
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};
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min = ~0;
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val = 0;
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en = 0;
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
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idx = 0;
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step = 2;
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if (!sel_rate[sel])
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continue;
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for (div = 2; div <= 98304; div += step) {
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diff = abs(target_rate - sel_rate[sel] / div);
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if (min > diff) {
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val = (sel << 8) | idx;
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min = diff;
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en = 1 << (sel + 1); /* fixme */
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}
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/*
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* step of 0_0000 / 0_0001 / 0_1101
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* are out of order
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*/
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if ((idx > 2) && (idx % 2))
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step *= 2;
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if (idx == 0x1c) {
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div += step;
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step *= 2;
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}
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idx++;
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}
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}
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if (min == ~0) {
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dev_err(dev, "no Input clock\n");
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return;
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}
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*target_val = val;
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if (target_en)
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*target_en = en;
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}
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static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate,
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u32 *in, u32 *out, u32 *en)
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{
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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unsigned int target_rate;
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u32 *target_val;
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u32 _in;
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u32 _out;
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u32 _en;
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/* default = SSI WS */
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_in =
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_out = rsnd_adg_ssi_ws_timing_gen2(io);
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target_rate = 0;
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target_val = NULL;
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_en = 0;
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if (runtime->rate != in_rate) {
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target_rate = out_rate;
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target_val = &_out;
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} else if (runtime->rate != out_rate) {
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target_rate = in_rate;
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target_val = &_in;
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}
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if (target_rate)
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__rsnd_adg_get_timesel_ratio(priv, io,
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target_rate,
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target_val, &_en);
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if (in)
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*in = _in;
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if (out)
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*out = _out;
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if (en)
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*en = _en;
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}
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
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struct rsnd_dai_stream *io)
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{
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@ -110,25 +212,24 @@ int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod,
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return 0;
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}
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static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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u32 timsel)
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int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int in_rate,
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unsigned int out_rate)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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int is_play = rsnd_io_is_play(io);
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u32 in, out;
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u32 mask, en;
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int id = rsnd_mod_id(src_mod);
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int shift = (id % 2) ? 16 : 0;
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u32 mask, ws;
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u32 in, out;
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rsnd_mod_confirm_src(src_mod);
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ws = rsnd_adg_ssi_ws_timing_gen2(io);
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in = (is_play) ? timsel : ws;
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out = (is_play) ? ws : timsel;
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rsnd_adg_get_timesel_ratio(priv, io,
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in_rate, out_rate,
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&in, &out, &en);
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in = in << shift;
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out = out << shift;
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@ -157,91 +258,12 @@ static int rsnd_adg_set_src_timsel_gen2(struct rsnd_mod *src_mod,
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break;
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}
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return 0;
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}
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int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int src_rate,
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unsigned int dst_rate)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct rsnd_mod *adg_mod = rsnd_mod_get(adg);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, step, ret;
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u32 val, en;
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unsigned int min, diff;
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unsigned int sel_rate [] = {
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clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
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adg->rbga_rate_for_441khz, /* 0011: RBGA */
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adg->rbgb_rate_for_48khz, /* 0100: RBGB */
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};
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rsnd_mod_confirm_src(src_mod);
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min = ~0;
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val = 0;
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en = 0;
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
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idx = 0;
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step = 2;
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if (!sel_rate[sel])
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continue;
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for (div = 2; div <= 98304; div += step) {
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diff = abs(src_rate - sel_rate[sel] / div);
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if (min > diff) {
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val = (sel << 8) | idx;
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min = diff;
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en = 1 << (sel + 1); /* fixme */
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}
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/*
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* step of 0_0000 / 0_0001 / 0_1101
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* are out of order
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*/
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if ((idx > 2) && (idx % 2))
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step *= 2;
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if (idx == 0x1c) {
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div += step;
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step *= 2;
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}
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idx++;
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}
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}
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if (min == ~0) {
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dev_err(dev, "no Input clock\n");
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return -EIO;
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}
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ret = rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
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if (ret < 0) {
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dev_err(dev, "timsel error\n");
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return ret;
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}
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rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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dev_dbg(dev, "convert rate %d <-> %d\n", src_rate, dst_rate);
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if (en)
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rsnd_mod_bset(adg_mod, DIV_EN, en, en);
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return 0;
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}
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int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io)
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{
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u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
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rsnd_mod_confirm_src(src_mod);
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return rsnd_adg_set_src_timsel_gen2(src_mod, io, val);
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}
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static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod);
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@ -446,12 +446,10 @@ int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod);
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate);
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int rsnd_adg_probe(struct rsnd_priv *priv);
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void rsnd_adg_remove(struct rsnd_priv *priv);
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int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
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int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod,
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struct rsnd_dai_stream *io,
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unsigned int src_rate,
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unsigned int dst_rate);
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int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
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struct rsnd_dai_stream *io);
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unsigned int in_rate,
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unsigned int out_rate);
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int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *mod,
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struct rsnd_dai_stream *io);
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@ -189,7 +189,7 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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u32 convert_rate = rsnd_src_convert_rate(io, mod);
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u32 fin, fout;
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u32 ifscr, fsrate, adinr;
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u32 cr, route;
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u32 bsdsr, bsisr;
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@ -198,13 +198,16 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
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if (!runtime)
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return;
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fin = rsnd_src_get_in_rate(priv, io);
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fout = rsnd_src_get_out_rate(priv, io);
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/* 6 - 1/6 are very enough ratio for SRC_BSDSR */
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if (!convert_rate)
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if (fin == fout)
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ratio = 0;
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else if (convert_rate > runtime->rate)
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ratio = 100 * convert_rate / runtime->rate;
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else if (fin > fout)
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ratio = 100 * fin / fout;
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else
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ratio = 100 * runtime->rate / convert_rate;
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ratio = 100 * fout / fin;
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if (ratio > 600) {
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dev_err(dev, "FSO/FSI ratio error\n");
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@ -222,9 +225,9 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
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*/
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ifscr = 0;
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fsrate = 0;
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if (convert_rate) {
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if (fin != fout) {
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ifscr = 1;
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fsrate = 0x0400000 / convert_rate * runtime->rate;
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fsrate = 0x0400000 / fout * fin;
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}
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/*
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@ -232,7 +235,7 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
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*/
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cr = 0x00011110;
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route = 0x0;
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if (convert_rate) {
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if (fin != fout) {
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route = 0x1;
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if (rsnd_src_sync_is_enabled(mod)) {
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@ -274,12 +277,7 @@ static void rsnd_src_set_convert_rate(struct rsnd_dai_stream *io,
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rsnd_mod_write(mod, SRC_O_BUSIF_MODE, 1);
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rsnd_mod_write(mod, SRC_BUSIF_DALIGN, rsnd_get_dalign(mod, io));
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if (convert_rate)
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rsnd_adg_set_convert_clk_gen2(mod, io,
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runtime->rate,
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convert_rate);
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else
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rsnd_adg_set_convert_timing_gen2(mod, io);
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rsnd_adg_set_src_timesel_gen2(mod, io, fin, fout);
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}
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static int rsnd_src_irq(struct rsnd_mod *mod,
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