[ARM] pxa: move camera (QCI) registers definition out of pxa-regs.h
Signed-off-by: Eric Miao <eric.miao@marvell.com> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>wifi-calibration
Eric Miao
parent
63e6552f7c
commit
013132cae8
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@ -611,101 +611,6 @@
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#ifdef CONFIG_PXA27x
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/* Camera Interface */
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#define CICR0 __REG(0x50000000)
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#define CICR1 __REG(0x50000004)
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#define CICR2 __REG(0x50000008)
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#define CICR3 __REG(0x5000000C)
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#define CICR4 __REG(0x50000010)
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#define CISR __REG(0x50000014)
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#define CIFR __REG(0x50000018)
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#define CITOR __REG(0x5000001C)
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#define CIBR0 __REG(0x50000028)
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#define CIBR1 __REG(0x50000030)
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#define CIBR2 __REG(0x50000038)
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#define CICR0_DMAEN (1 << 31) /* DMA request enable */
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#define CICR0_PAR_EN (1 << 30) /* Parity enable */
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#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
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#define CICR0_ENB (1 << 28) /* Camera interface enable */
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#define CICR0_DIS (1 << 27) /* Camera interface disable */
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#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
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#define CICR0_TOM (1 << 9) /* Time-out mask */
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#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
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#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
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#define CICR0_EOLM (1 << 6) /* End-of-line mask */
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#define CICR0_PERRM (1 << 5) /* Parity-error mask */
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#define CICR0_QDM (1 << 4) /* Quick-disable mask */
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#define CICR0_CDM (1 << 3) /* Disable-done mask */
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#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
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#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
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#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
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#define CICR1_TBIT (1 << 31) /* Transparency bit */
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#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
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#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
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#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
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#define CICR1_RGB_F (1 << 11) /* RGB format */
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#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
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#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
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#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
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#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
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#define CICR1_DW (0x7 << 0) /* Data width mask */
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#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
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wait count mask */
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#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
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wait count mask */
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#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
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#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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wait count mask */
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#define CICR2_FSW (0x7 << 0) /* Frame stabilization
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wait count mask */
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#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
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wait count mask */
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#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
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wait count mask */
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#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
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#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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wait count mask */
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#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
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#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
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#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
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#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
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#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
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#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
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#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
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#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
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#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
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#define CISR_FTO (1 << 15) /* FIFO time-out */
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#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
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#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
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#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
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#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
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#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
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#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
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#define CISR_EOL (1 << 8) /* End of line */
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#define CISR_PAR_ERR (1 << 7) /* Parity error */
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#define CISR_CQD (1 << 6) /* Camera interface quick disable */
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#define CISR_CDD (1 << 5) /* Camera interface disable done */
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#define CISR_SOF (1 << 4) /* Start of frame */
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#define CISR_EOF (1 << 3) /* End of frame */
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#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
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#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
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#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
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#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
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#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
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#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
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#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
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#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
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#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
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#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
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#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
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#define SRAM_SIZE 0x40000 /* 4x64K */
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#define SRAM_MEM_PHYS 0x5C000000
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@ -39,6 +39,8 @@
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#include <mach/pxa-regs.h>
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#include <mach/camera.h>
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#include "pxa_camera.h"
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#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
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#define PXA_CAM_DRV_NAME "pxa27x-camera"
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@ -0,0 +1,95 @@
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/* Camera Interface */
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#define CICR0 __REG(0x50000000)
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#define CICR1 __REG(0x50000004)
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#define CICR2 __REG(0x50000008)
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#define CICR3 __REG(0x5000000C)
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#define CICR4 __REG(0x50000010)
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#define CISR __REG(0x50000014)
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#define CIFR __REG(0x50000018)
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#define CITOR __REG(0x5000001C)
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#define CIBR0 __REG(0x50000028)
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#define CIBR1 __REG(0x50000030)
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#define CIBR2 __REG(0x50000038)
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#define CICR0_DMAEN (1 << 31) /* DMA request enable */
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#define CICR0_PAR_EN (1 << 30) /* Parity enable */
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#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
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#define CICR0_ENB (1 << 28) /* Camera interface enable */
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#define CICR0_DIS (1 << 27) /* Camera interface disable */
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#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
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#define CICR0_TOM (1 << 9) /* Time-out mask */
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#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
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#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
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#define CICR0_EOLM (1 << 6) /* End-of-line mask */
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#define CICR0_PERRM (1 << 5) /* Parity-error mask */
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#define CICR0_QDM (1 << 4) /* Quick-disable mask */
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#define CICR0_CDM (1 << 3) /* Disable-done mask */
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#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
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#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
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#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
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#define CICR1_TBIT (1 << 31) /* Transparency bit */
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#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
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#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
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#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
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#define CICR1_RGB_F (1 << 11) /* RGB format */
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#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
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#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
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#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
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#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
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#define CICR1_DW (0x7 << 0) /* Data width mask */
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#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
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wait count mask */
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#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
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wait count mask */
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#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
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#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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wait count mask */
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#define CICR2_FSW (0x7 << 0) /* Frame stabilization
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wait count mask */
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#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
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wait count mask */
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#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
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wait count mask */
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#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
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#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
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wait count mask */
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#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
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#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
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#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
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#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
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#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
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#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
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#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
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#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
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#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
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#define CISR_FTO (1 << 15) /* FIFO time-out */
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#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
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#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
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#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
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#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
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#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
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#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
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#define CISR_EOL (1 << 8) /* End of line */
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#define CISR_PAR_ERR (1 << 7) /* Parity error */
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#define CISR_CQD (1 << 6) /* Camera interface quick disable */
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#define CISR_CDD (1 << 5) /* Camera interface disable done */
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#define CISR_SOF (1 << 4) /* Start of frame */
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#define CISR_EOF (1 << 3) /* End of frame */
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#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
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#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
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#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
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#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
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#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
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#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
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#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
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#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
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#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
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#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
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#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
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