x86, ds: support Core i7
Add debug store support for Core i7. Core i7 adds a reset value for each performance counter and a new PEBS record format. Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Cc: roland@redhat.com Cc: eranian@googlemail.com Cc: oleg@redhat.com Cc: juan.villacis@intel.com Cc: ak@linux.jf.intel.com LKML-Reference: <20090403144607.088997000@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -234,8 +234,12 @@ struct bts_trace {
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struct pebs_trace {
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struct ds_trace ds;
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/* the PEBS reset value */
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unsigned long long reset_value;
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/* the number of valid counters in the below array */
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unsigned int counters;
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#define MAX_PEBS_COUNTERS 4
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/* the counter reset value */
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unsigned long long counter_reset[MAX_PEBS_COUNTERS];
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};
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@ -270,9 +274,11 @@ extern int ds_reset_pebs(struct pebs_tracer *tracer);
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* Returns 0 on success; -Eerrno on error
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*
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* tracer: the tracer handle returned from ds_request_pebs()
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* counter: the index of the counter
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* value: the new counter reset value
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*/
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extern int ds_set_pebs_reset(struct pebs_tracer *tracer, u64 value);
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extern int ds_set_pebs_reset(struct pebs_tracer *tracer,
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unsigned int counter, u64 value);
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/*
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* Initialization
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@ -44,6 +44,9 @@ struct ds_configuration {
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/* The size of a BTS/PEBS record in bytes: */
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unsigned char sizeof_rec[2];
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/* The number of pebs counter reset values in the DS structure. */
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unsigned char nr_counter_reset;
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/* Control bit-masks indexed by enum ds_feature: */
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unsigned long ctl[dsf_ctl_max];
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};
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@ -51,7 +54,7 @@ static struct ds_configuration ds_cfg __read_mostly;
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/* Maximal size of a DS configuration: */
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#define MAX_SIZEOF_DS (12 * 8)
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#define MAX_SIZEOF_DS 0x80
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/* Maximal size of a BTS record: */
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#define MAX_SIZEOF_BTS (3 * 8)
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@ -59,6 +62,12 @@ static struct ds_configuration ds_cfg __read_mostly;
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/* BTS and PEBS buffer alignment: */
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#define DS_ALIGNMENT (1 << 3)
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/* Number of buffer pointers in DS: */
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#define NUM_DS_PTR_FIELDS 8
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/* Size of a pebs reset value in DS: */
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#define PEBS_RESET_FIELD_SIZE 8
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/* Mask of control bits in the DS MSR register: */
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#define BTS_CONTROL \
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( ds_cfg.ctl[dsf_bts] | \
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@ -1164,9 +1173,12 @@ const struct pebs_trace *ds_read_pebs(struct pebs_tracer *tracer)
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return NULL;
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ds_read_config(tracer->ds.context, &tracer->trace.ds, ds_pebs);
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tracer->trace.reset_value =
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*(u64 *)(tracer->ds.context->ds +
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(ds_cfg.sizeof_ptr_field * 8));
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tracer->trace.counters = ds_cfg.nr_counter_reset;
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memcpy(tracer->trace.counter_reset,
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tracer->ds.context->ds +
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(NUM_DS_PTR_FIELDS * ds_cfg.sizeof_ptr_field),
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ds_cfg.nr_counter_reset * PEBS_RESET_FIELD_SIZE);
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return &tracer->trace;
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}
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@ -1197,13 +1209,18 @@ int ds_reset_pebs(struct pebs_tracer *tracer)
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return 0;
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}
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int ds_set_pebs_reset(struct pebs_tracer *tracer, u64 value)
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int ds_set_pebs_reset(struct pebs_tracer *tracer,
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unsigned int counter, u64 value)
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{
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if (!tracer)
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return -EINVAL;
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if (ds_cfg.nr_counter_reset < counter)
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return -EINVAL;
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*(u64 *)(tracer->ds.context->ds +
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(ds_cfg.sizeof_ptr_field * 8)) = value;
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(NUM_DS_PTR_FIELDS * ds_cfg.sizeof_ptr_field) +
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(counter * PEBS_RESET_FIELD_SIZE)) = value;
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return 0;
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}
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@ -1213,16 +1230,26 @@ static const struct ds_configuration ds_cfg_netburst = {
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.ctl[dsf_bts] = (1 << 2) | (1 << 3),
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.ctl[dsf_bts_kernel] = (1 << 5),
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.ctl[dsf_bts_user] = (1 << 6),
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.nr_counter_reset = 1,
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};
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static const struct ds_configuration ds_cfg_pentium_m = {
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.name = "Pentium M",
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.ctl[dsf_bts] = (1 << 6) | (1 << 7),
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.nr_counter_reset = 1,
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};
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static const struct ds_configuration ds_cfg_core2_atom = {
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.name = "Core 2/Atom",
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.ctl[dsf_bts] = (1 << 6) | (1 << 7),
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.ctl[dsf_bts_kernel] = (1 << 9),
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.ctl[dsf_bts_user] = (1 << 10),
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.nr_counter_reset = 1,
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};
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static const struct ds_configuration ds_cfg_core_i7 = {
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.name = "Core i7",
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.ctl[dsf_bts] = (1 << 6) | (1 << 7),
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.ctl[dsf_bts_kernel] = (1 << 9),
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.ctl[dsf_bts_user] = (1 << 10),
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.nr_counter_reset = 4,
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};
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static void
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@ -1239,6 +1266,32 @@ ds_configure(const struct ds_configuration *cfg,
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nr_pebs_fields = 18;
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#endif
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/*
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* Starting with version 2, architectural performance
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* monitoring supports a format specifier.
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*/
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if ((cpuid_eax(0xa) & 0xff) > 1) {
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unsigned long perf_capabilities, format;
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rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_capabilities);
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format = (perf_capabilities >> 8) & 0xf;
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switch (format) {
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case 0:
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nr_pebs_fields = 18;
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break;
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case 1:
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nr_pebs_fields = 22;
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break;
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default:
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printk(KERN_INFO
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"[ds] unknown PEBS format: %lu\n", format);
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nr_pebs_fields = 0;
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break;
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}
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}
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memset(&ds_cfg, 0, sizeof(ds_cfg));
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ds_cfg = *cfg;
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@ -1262,7 +1315,7 @@ ds_configure(const struct ds_configuration *cfg,
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printk("bts/pebs record: %u/%u bytes\n",
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ds_cfg.sizeof_rec[ds_bts], ds_cfg.sizeof_rec[ds_pebs]);
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WARN_ON_ONCE(MAX_SIZEOF_DS < (12 * ds_cfg.sizeof_ptr_field));
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WARN_ON_ONCE(MAX_PEBS_COUNTERS < ds_cfg.nr_counter_reset);
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}
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void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
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@ -1284,6 +1337,8 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c)
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ds_configure(&ds_cfg_core2_atom, c);
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break;
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case 0x1a: /* Core i7 */
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ds_configure(&ds_cfg_core_i7, c);
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break;
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default:
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/* Sorry, don't know about them. */
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break;
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