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iwlwifi: pcie: don't read INTA register in ICT IRQ handler

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There's no reason to read the INTA register in the ICT IRQ
handler, this interrupt mechanism is designed to not have
to read as many registers as the regular one. Not reading
the INTA register gives a significant performance/CPU use
improvement.

Since we still want to get this info, fetch it only if
the ISR debug level is enabled.

Reviewed-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
Johannes Berg 2013-06-11 21:12:29 +02:00
parent 68972c46f2
commit 01911dab97
1 changed files with 8 additions and 4 deletions
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12
drivers/net/wireless/iwlwifi/pcie/rx.c
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@ -1198,7 +1198,7 @@ irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
{
struct iwl_trans *trans = data;
struct iwl_trans_pcie *trans_pcie;
u32 inta, inta_mask;
u32 inta;
u32 val = 0;
u32 read;
unsigned long flags;
@ -1226,7 +1226,6 @@ irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
* If we have something to service, the tasklet will re-enable ints.
* If we *don't* have something, we'll re-enable before leaving here.
*/
inta_mask = iwl_read32(trans, CSR_INT_MASK);
iwl_write32(trans, CSR_INT_MASK, 0x00000000);
/* Ignore interrupt if there's nothing in NIC to service.
@ -1271,8 +1270,13 @@ irqreturn_t iwl_pcie_isr_ict(int irq, void *data)
val |= 0x8000;
inta = (0xff & val) | ((0xff00 & val) << 16);
IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
inta, inta_mask, val);
IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
inta, trans_pcie->inta_mask, val);
#ifdef CONFIG_IWLWIFI_DEBUG
if (iwl_have_debug_level(IWL_DL_ISR))
IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
iwl_read32(trans, CSR_INT_MASK));
#endif
inta &= trans_pcie->inta_mask;
trans_pcie->inta |= inta;