clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code
This patch uses the samsung_cmu_register_one() to simplify code for Exynos4415. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
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@ -113,19 +113,6 @@
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#define DIV_CPU0 0x14500
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#define DIV_CPU1 0x14504
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enum exynos4415_plls {
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apll, epll, g3d_pll, isp_pll, disp_pll,
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nr_plls,
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};
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static struct samsung_clk_provider *exynos4415_ctx;
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/*
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* Support for CMU save/restore across system suspends
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*/
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos4415_clk_regs;
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static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
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SRC_LEFTBUS,
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DIV_LEFTBUS,
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@ -219,41 +206,6 @@ static unsigned long exynos4415_cmu_clk_regs[] __initdata = {
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DIV_CPU1,
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};
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static int exynos4415_clk_suspend(void)
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{
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samsung_clk_save(exynos4415_ctx->reg_base, exynos4415_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_clk_regs));
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return 0;
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}
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static void exynos4415_clk_resume(void)
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{
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samsung_clk_restore(exynos4415_ctx->reg_base, exynos4415_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_clk_regs));
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}
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static struct syscore_ops exynos4415_clk_syscore_ops = {
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.suspend = exynos4415_clk_suspend,
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.resume = exynos4415_clk_resume,
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};
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static void exynos4415_clk_sleep_init(void)
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{
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exynos4415_clk_regs =
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samsung_clk_alloc_reg_dump(exynos4415_cmu_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_clk_regs));
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if (!exynos4415_clk_regs) {
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pr_warn("%s: Failed to allocate sleep save data\n", __func__);
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return;
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}
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register_syscore_ops(&exynos4415_clk_syscore_ops);
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}
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#else
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static inline void exynos4415_clk_sleep_init(void) { }
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#endif
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/* list of all parent clock list */
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PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
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@ -959,56 +911,40 @@ static struct samsung_pll_rate_table exynos4415_epll_rates[] = {
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{ /* sentinel */ }
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};
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static struct samsung_pll_clock exynos4415_plls[nr_plls] __initdata = {
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[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, NULL),
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[epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, NULL),
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[g3d_pll] = PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll",
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"mout_g3d_pllsrc", G3D_PLL_LOCK, G3D_PLL_CON0, NULL),
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[isp_pll] = PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
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ISP_PLL_LOCK, ISP_PLL_CON0, NULL),
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[disp_pll] = PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
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"fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, NULL),
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static struct samsung_pll_clock exynos4415_plls[] __initdata = {
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PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
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APLL_LOCK, APLL_CON0, exynos4415_pll_rates),
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PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
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EPLL_LOCK, EPLL_CON0, exynos4415_epll_rates),
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PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
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G3D_PLL_LOCK, G3D_PLL_CON0, exynos4415_pll_rates),
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PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
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ISP_PLL_LOCK, ISP_PLL_CON0, exynos4415_pll_rates),
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PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
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"fin_pll", DISP_PLL_LOCK, DISP_PLL_CON0, exynos4415_pll_rates),
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};
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static struct samsung_cmu_info cmu_info __initdata = {
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.pll_clks = exynos4415_plls,
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.nr_pll_clks = ARRAY_SIZE(exynos4415_plls),
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.mux_clks = exynos4415_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(exynos4415_mux_clks),
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.div_clks = exynos4415_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos4415_div_clks),
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.gate_clks = exynos4415_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(exynos4415_gate_clks),
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.fixed_clks = exynos4415_fixed_rate_clks,
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.nr_fixed_clks = ARRAY_SIZE(exynos4415_fixed_rate_clks),
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.fixed_factor_clks = exynos4415_fixed_factor_clks,
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.nr_fixed_factor_clks = ARRAY_SIZE(exynos4415_fixed_factor_clks),
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.nr_clk_ids = CLK_NR_CLKS,
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.clk_regs = exynos4415_cmu_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_clk_regs),
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};
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static void __init exynos4415_cmu_init(struct device_node *np)
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{
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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exynos4415_ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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if (!exynos4415_ctx)
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panic("%s: unable to allocate context.\n", __func__);
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exynos4415_plls[apll].rate_table = exynos4415_pll_rates;
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exynos4415_plls[epll].rate_table = exynos4415_epll_rates;
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exynos4415_plls[g3d_pll].rate_table = exynos4415_pll_rates;
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exynos4415_plls[isp_pll].rate_table = exynos4415_pll_rates;
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exynos4415_plls[disp_pll].rate_table = exynos4415_pll_rates;
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samsung_clk_register_fixed_factor(exynos4415_ctx,
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exynos4415_fixed_factor_clks,
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ARRAY_SIZE(exynos4415_fixed_factor_clks));
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samsung_clk_register_fixed_rate(exynos4415_ctx,
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exynos4415_fixed_rate_clks,
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ARRAY_SIZE(exynos4415_fixed_rate_clks));
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samsung_clk_register_pll(exynos4415_ctx, exynos4415_plls,
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ARRAY_SIZE(exynos4415_plls), reg_base);
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samsung_clk_register_mux(exynos4415_ctx, exynos4415_mux_clks,
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ARRAY_SIZE(exynos4415_mux_clks));
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samsung_clk_register_div(exynos4415_ctx, exynos4415_div_clks,
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ARRAY_SIZE(exynos4415_div_clks));
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samsung_clk_register_gate(exynos4415_ctx, exynos4415_gate_clks,
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ARRAY_SIZE(exynos4415_gate_clks));
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exynos4415_clk_sleep_init();
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samsung_clk_of_add_provider(np, exynos4415_ctx);
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samsung_cmu_register_one(np, &cmu_info);
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}
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CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
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@ -1027,16 +963,6 @@ CLK_OF_DECLARE(exynos4415_cmu, "samsung,exynos4415-cmu", exynos4415_cmu_init);
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#define SRC_DMC 0x300
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#define DIV_DMC1 0x504
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enum exynos4415_dmc_plls {
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mpll, bpll,
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nr_dmc_plls,
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};
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static struct samsung_clk_provider *exynos4415_dmc_ctx;
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#ifdef CONFIG_PM_SLEEP
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static struct samsung_clk_reg_dump *exynos4415_dmc_clk_regs;
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static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
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MPLL_LOCK,
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MPLL_CON0,
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@ -1050,42 +976,6 @@ static unsigned long exynos4415_cmu_dmc_clk_regs[] __initdata = {
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DIV_DMC1,
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};
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static int exynos4415_dmc_clk_suspend(void)
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{
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samsung_clk_save(exynos4415_dmc_ctx->reg_base,
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exynos4415_dmc_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
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return 0;
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}
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static void exynos4415_dmc_clk_resume(void)
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{
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samsung_clk_restore(exynos4415_dmc_ctx->reg_base,
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exynos4415_dmc_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
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}
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static struct syscore_ops exynos4415_dmc_clk_syscore_ops = {
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.suspend = exynos4415_dmc_clk_suspend,
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.resume = exynos4415_dmc_clk_resume,
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};
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static void exynos4415_dmc_clk_sleep_init(void)
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{
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exynos4415_dmc_clk_regs =
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samsung_clk_alloc_reg_dump(exynos4415_cmu_dmc_clk_regs,
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ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs));
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if (!exynos4415_dmc_clk_regs) {
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pr_warn("%s: Failed to allocate sleep save data\n", __func__);
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return;
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}
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register_syscore_ops(&exynos4415_dmc_clk_syscore_ops);
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}
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#else
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static inline void exynos4415_dmc_clk_sleep_init(void) { }
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#endif /* CONFIG_PM_SLEEP */
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PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
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PNAME(mout_bpll_p) = { "fin_pll", "fout_bpll", };
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PNAME(mbpll_p) = { "mout_mpll", "mout_bpll", };
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@ -1107,38 +997,28 @@ static struct samsung_div_clock exynos4415_dmc_div_clks[] __initdata = {
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DIV(CLK_DMC_DIV_MPLL_PRE, "div_mpll_pre", "mout_mpll", DIV_DMC1, 8, 2),
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};
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static struct samsung_pll_clock exynos4415_dmc_plls[nr_dmc_plls] __initdata = {
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[mpll] = PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
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MPLL_LOCK, MPLL_CON0, NULL),
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[bpll] = PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
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BPLL_LOCK, BPLL_CON0, NULL),
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static struct samsung_pll_clock exynos4415_dmc_plls[] __initdata = {
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PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
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MPLL_LOCK, MPLL_CON0, exynos4415_pll_rates),
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PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
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BPLL_LOCK, BPLL_CON0, exynos4415_pll_rates),
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};
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static struct samsung_cmu_info cmu_dmc_info __initdata = {
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.pll_clks = exynos4415_dmc_plls,
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.nr_pll_clks = ARRAY_SIZE(exynos4415_dmc_plls),
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.mux_clks = exynos4415_dmc_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(exynos4415_dmc_mux_clks),
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.div_clks = exynos4415_dmc_div_clks,
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.nr_div_clks = ARRAY_SIZE(exynos4415_dmc_div_clks),
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.nr_clk_ids = NR_CLKS_DMC,
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.clk_regs = exynos4415_cmu_dmc_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(exynos4415_cmu_dmc_clk_regs),
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};
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static void __init exynos4415_cmu_dmc_init(struct device_node *np)
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{
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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exynos4415_dmc_ctx = samsung_clk_init(np, reg_base, NR_CLKS_DMC);
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if (!exynos4415_dmc_ctx)
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panic("%s: unable to allocate context.\n", __func__);
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exynos4415_dmc_plls[mpll].rate_table = exynos4415_pll_rates;
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exynos4415_dmc_plls[bpll].rate_table = exynos4415_pll_rates;
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samsung_clk_register_pll(exynos4415_dmc_ctx, exynos4415_dmc_plls,
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ARRAY_SIZE(exynos4415_dmc_plls), reg_base);
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samsung_clk_register_mux(exynos4415_dmc_ctx, exynos4415_dmc_mux_clks,
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ARRAY_SIZE(exynos4415_dmc_mux_clks));
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samsung_clk_register_div(exynos4415_dmc_ctx, exynos4415_dmc_div_clks,
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ARRAY_SIZE(exynos4415_dmc_div_clks));
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exynos4415_dmc_clk_sleep_init();
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samsung_clk_of_add_provider(np, exynos4415_dmc_ctx);
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samsung_cmu_register_one(np, &cmu_dmc_info);
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}
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CLK_OF_DECLARE(exynos4415_cmu_dmc, "samsung,exynos4415-cmu-dmc",
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exynos4415_cmu_dmc_init);
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