ath5k: move checks and stats into new function
Create a new function ath5k_receive_frame_ok() which checks for errors, updates error statistics and tells us if we want to further "receive" this frame or not. This way we can avoid a goto and have a cleaner separation between buffer handling and other things. Signed-off-by: Bruno Randolf <br1@einfach.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1973,6 +1973,61 @@ ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
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ieee80211_rx(sc->hw, skb);
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}
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/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
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*
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* Check if we want to further process this frame or not. Also update
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* statistics. Return true if we want this frame, false if not.
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*/
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static bool
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ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
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{
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sc->stats.rx_all_count++;
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if (unlikely(rs->rs_status)) {
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if (rs->rs_status & AR5K_RXERR_CRC)
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sc->stats.rxerr_crc++;
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if (rs->rs_status & AR5K_RXERR_FIFO)
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sc->stats.rxerr_fifo++;
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if (rs->rs_status & AR5K_RXERR_PHY) {
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sc->stats.rxerr_phy++;
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if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
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sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
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return false;
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}
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if (rs->rs_status & AR5K_RXERR_DECRYPT) {
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/*
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* Decrypt error. If the error occurred
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* because there was no hardware key, then
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* let the frame through so the upper layers
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* can process it. This is necessary for 5210
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* parts which have no way to setup a ``clear''
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* key cache entry.
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*
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* XXX do key cache faulting
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*/
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sc->stats.rxerr_decrypt++;
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if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
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!(rs->rs_status & AR5K_RXERR_CRC))
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return true;
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}
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if (rs->rs_status & AR5K_RXERR_MIC) {
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sc->stats.rxerr_mic++;
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return true;
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}
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/* let crypto-error packets fall through in MNTR */
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if ((rs->rs_status & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
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sc->opmode != NL80211_IFTYPE_MONITOR)
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return false;
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}
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if (unlikely(rs->rs_more)) {
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sc->stats.rxerr_jumbo++;
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return false;
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}
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return true;
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}
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static void
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ath5k_tasklet_rx(unsigned long data)
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{
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@ -2010,70 +2065,27 @@ ath5k_tasklet_rx(unsigned long data)
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break;
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}
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sc->stats.rx_all_count++;
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if (ath5k_receive_frame_ok(sc, &rs)) {
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next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
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if (unlikely(rs.rs_status)) {
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if (rs.rs_status & AR5K_RXERR_CRC)
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sc->stats.rxerr_crc++;
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if (rs.rs_status & AR5K_RXERR_FIFO)
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sc->stats.rxerr_fifo++;
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if (rs.rs_status & AR5K_RXERR_PHY) {
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sc->stats.rxerr_phy++;
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if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
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sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
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/*
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* If we can't replace bf->skb with a new skb under
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* memory pressure, just skip this packet
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*/
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if (!next_skb)
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goto next;
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}
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if (rs.rs_status & AR5K_RXERR_DECRYPT) {
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/*
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* Decrypt error. If the error occurred
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* because there was no hardware key, then
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* let the frame through so the upper layers
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* can process it. This is necessary for 5210
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* parts which have no way to setup a ``clear''
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* key cache entry.
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*
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* XXX do key cache faulting
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*/
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sc->stats.rxerr_decrypt++;
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if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
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!(rs.rs_status & AR5K_RXERR_CRC))
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goto accept;
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}
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if (rs.rs_status & AR5K_RXERR_MIC) {
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sc->stats.rxerr_mic++;
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goto accept;
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}
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/* let crypto-error packets fall through in MNTR */
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if ((rs.rs_status &
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~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
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sc->opmode != NL80211_IFTYPE_MONITOR)
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goto next;
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pci_unmap_single(sc->pdev, bf->skbaddr,
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common->rx_bufsize,
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PCI_DMA_FROMDEVICE);
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skb_put(skb, rs.rs_datalen);
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ath5k_receive_frame(sc, skb, &rs);
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bf->skb = next_skb;
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bf->skbaddr = next_skb_addr;
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}
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if (unlikely(rs.rs_more)) {
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sc->stats.rxerr_jumbo++;
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goto next;
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}
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accept:
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next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
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/*
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* If we can't replace bf->skb with a new skb under memory
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* pressure, just skip this packet
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*/
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if (!next_skb)
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goto next;
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pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
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PCI_DMA_FROMDEVICE);
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skb_put(skb, rs.rs_datalen);
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ath5k_receive_frame(sc, skb, &rs);
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bf->skb = next_skb;
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bf->skbaddr = next_skb_addr;
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next:
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list_move_tail(&bf->list, &sc->rxbuf);
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} while (ath5k_rxbuf_setup(sc, bf) == 0);
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@ -2082,8 +2094,6 @@ unlock:
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}
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/*************\
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* TX Handling *
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\*************/
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