lan78xx: add LAN7801 MAC only support
Add LAN7801 MAC only support with phy fixup functions. Signed-off-by: Woojung Huh <woojung.huh@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -114,6 +114,11 @@ config USB_LAN78XX
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help
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This option adds support for Microchip LAN78XX based USB 2
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& USB 3 10/100/1000 Ethernet adapters.
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LAN7800 : USB 3 to 10/100/1000 Ethernet adapter
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LAN7850 : USB 2 to 10/100/1000 Ethernet adapter
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LAN7801 : USB 3 to 10/100/1000 Ethernet adapter (MAC only)
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Proper PHY driver is required for LAN7801.
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To compile this driver as a module, choose M here: the
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module will be called lan78xx.
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@ -40,7 +40,7 @@
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#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
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#define DRIVER_DESC "LAN78XX USB 3.0 Gigabit Ethernet Devices"
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#define DRIVER_NAME "lan78xx"
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#define DRIVER_VERSION "1.0.5"
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#define DRIVER_VERSION "1.0.6"
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#define TX_TIMEOUT_JIFFIES (5 * HZ)
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#define THROTTLE_JIFFIES (HZ / 8)
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@ -67,6 +67,7 @@
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#define LAN78XX_USB_VENDOR_ID (0x0424)
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#define LAN7800_USB_PRODUCT_ID (0x7800)
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#define LAN7850_USB_PRODUCT_ID (0x7850)
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#define LAN7801_USB_PRODUCT_ID (0x7801)
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#define LAN78XX_EEPROM_MAGIC (0x78A5)
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#define LAN78XX_OTP_MAGIC (0x78F3)
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@ -390,6 +391,7 @@ struct lan78xx_net {
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u32 chipid;
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u32 chiprev;
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struct mii_bus *mdiobus;
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phy_interface_t interface;
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int fc_autoneg;
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u8 fc_request_control;
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@ -400,6 +402,10 @@ struct lan78xx_net {
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struct irq_domain_data domain_data;
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};
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/* define external phy id */
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#define PHY_LAN8835 (0x0007C130)
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#define PHY_KSZ9031RNX (0x00221620)
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/* use ethtool to change the level for any given device */
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static int msg_level = -1;
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module_param(msg_level, int, 0);
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@ -1697,6 +1703,7 @@ static int lan78xx_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
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done:
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mutex_unlock(&dev->phy_mutex);
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usb_autopm_put_interface(dev->intf);
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return ret;
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}
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@ -1759,6 +1766,10 @@ static int lan78xx_mdio_init(struct lan78xx_net *dev)
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/* set to internal PHY id */
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dev->mdiobus->phy_mask = ~(1 << 1);
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break;
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case ID_REV_CHIP_ID_7801_:
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/* scan thru PHYAD[2..0] */
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dev->mdiobus->phy_mask = ~(0xFF);
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break;
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}
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ret = mdiobus_register(dev->mdiobus);
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@ -1933,6 +1944,47 @@ static void lan78xx_remove_irq_domain(struct lan78xx_net *dev)
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dev->domain_data.irqdomain = NULL;
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}
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static int lan8835_fixup(struct phy_device *phydev)
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{
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int buf;
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int ret;
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struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
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/* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */
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buf = phy_read_mmd_indirect(phydev, 0x8010, 3);
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buf &= ~0x1800;
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buf |= 0x0800;
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phy_write_mmd_indirect(phydev, 0x8010, 3, buf);
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/* RGMII MAC TXC Delay Enable */
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ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
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MAC_RGMII_ID_TXC_DELAY_EN_);
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/* RGMII TX DLL Tune Adjust */
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ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
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dev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
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return 1;
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}
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static int ksz9031rnx_fixup(struct phy_device *phydev)
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{
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struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
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/* Micrel9301RNX PHY configuration */
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/* RGMII Control Signal Pad Skew */
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phy_write_mmd_indirect(phydev, 4, 2, 0x0077);
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/* RGMII RX Data Pad Skew */
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phy_write_mmd_indirect(phydev, 5, 2, 0x7777);
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/* RGMII RX Clock Pad Skew */
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phy_write_mmd_indirect(phydev, 8, 2, 0x1FF);
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dev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
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return 1;
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}
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static int lan78xx_phy_init(struct lan78xx_net *dev)
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{
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int ret;
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@ -1945,6 +1997,42 @@ static int lan78xx_phy_init(struct lan78xx_net *dev)
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return -EIO;
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}
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if ((dev->chipid == ID_REV_CHIP_ID_7800_) ||
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(dev->chipid == ID_REV_CHIP_ID_7850_)) {
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phydev->is_internal = true;
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dev->interface = PHY_INTERFACE_MODE_GMII;
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} else if (dev->chipid == ID_REV_CHIP_ID_7801_) {
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if (!phydev->drv) {
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netdev_err(dev->net, "no PHY driver found\n");
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return -EIO;
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}
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dev->interface = PHY_INTERFACE_MODE_RGMII;
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/* external PHY fixup for KSZ9031RNX */
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ret = phy_register_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0,
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ksz9031rnx_fixup);
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if (ret < 0) {
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netdev_err(dev->net, "fail to register fixup\n");
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return ret;
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}
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/* external PHY fixup for LAN8835 */
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ret = phy_register_fixup_for_uid(PHY_LAN8835, 0xfffffff0,
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lan8835_fixup);
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if (ret < 0) {
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netdev_err(dev->net, "fail to register fixup\n");
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return ret;
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}
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/* add more external PHY fixup here if needed */
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phydev->is_internal = false;
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} else {
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netdev_err(dev->net, "unknown ID found\n");
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ret = -EIO;
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goto error;
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}
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/* if phyirq is not set, use polling mode in phylib */
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if (dev->domain_data.phyirq > 0)
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phydev->irq = dev->domain_data.phyirq;
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@ -1957,7 +2045,7 @@ static int lan78xx_phy_init(struct lan78xx_net *dev)
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ret = phy_connect_direct(dev->net, phydev,
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lan78xx_link_status_change,
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PHY_INTERFACE_MODE_GMII);
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dev->interface);
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if (ret) {
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netdev_err(dev->net, "can't attach PHY to %s\n",
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dev->mdiobus->id);
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@ -1982,6 +2070,12 @@ static int lan78xx_phy_init(struct lan78xx_net *dev)
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netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
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return 0;
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error:
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phy_unregister_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0);
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phy_unregister_fixup_for_uid(PHY_LAN8835, 0xfffffff0);
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return ret;
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}
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static int lan78xx_set_rx_max_frame_length(struct lan78xx_net *dev, int size)
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@ -2338,6 +2432,9 @@ static int lan78xx_reset(struct lan78xx_net *dev)
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} while ((buf & PMT_CTL_PHY_RST_) || !(buf & PMT_CTL_READY_));
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ret = lan78xx_read_reg(dev, MAC_CR, &buf);
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/* LAN7801 only has RGMII mode */
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if (dev->chipid == ID_REV_CHIP_ID_7801_)
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buf &= ~MAC_CR_GMII_EN_;
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buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
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ret = lan78xx_write_reg(dev, MAC_CR, buf);
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@ -2464,8 +2561,12 @@ static int lan78xx_stop(struct net_device *net)
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if (timer_pending(&dev->stat_monitor))
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del_timer_sync(&dev->stat_monitor);
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phy_unregister_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0);
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phy_unregister_fixup_for_uid(PHY_LAN8835, 0xfffffff0);
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phy_stop(net->phydev);
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phy_disconnect(net->phydev);
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net->phydev = NULL;
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clear_bit(EVENT_DEV_OPEN, &dev->flags);
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@ -3888,6 +3989,10 @@ static const struct usb_device_id products[] = {
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/* LAN7850 USB Gigabit Ethernet Device */
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USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7850_USB_PRODUCT_ID),
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},
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{
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/* LAN7801 USB Gigabit Ethernet Device */
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USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7801_USB_PRODUCT_ID),
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},
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{},
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};
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MODULE_DEVICE_TABLE(usb, products);
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@ -108,6 +108,7 @@
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#define ID_REV_CHIP_REV_MASK_ (0x0000FFFF)
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#define ID_REV_CHIP_ID_7800_ (0x7800)
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#define ID_REV_CHIP_ID_7850_ (0x7850)
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#define ID_REV_CHIP_ID_7801_ (0x7801)
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#define FPGA_REV (0x04)
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#define FPGA_REV_MINOR_MASK_ (0x0000FF00)
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@ -550,6 +551,7 @@
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#define LTM_INACTIVE1_TIMER10_ (0x0000FFFF)
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#define MAC_CR (0x100)
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#define MAC_CR_GMII_EN_ (0x00080000)
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#define MAC_CR_EEE_TX_CLK_STOP_EN_ (0x00040000)
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#define MAC_CR_EEE_EN_ (0x00020000)
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#define MAC_CR_EEE_TLAR_EN_ (0x00010000)
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@ -787,6 +789,18 @@
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#define PHY_DEV_ID_MODEL_MASK_ (0x0FC00000)
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#define PHY_DEV_ID_OUI_MASK_ (0x003FFFFF)
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#define RGMII_TX_BYP_DLL (0x708)
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#define RGMII_TX_BYP_DLL_TX_TUNE_ADJ_MASK_ (0x000FC00)
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#define RGMII_TX_BYP_DLL_TX_TUNE_SEL_MASK_ (0x00003F0)
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#define RGMII_TX_BYP_DLL_TX_DLL_RESET_ (0x0000002)
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#define RGMII_TX_BYP_DLL_TX_DLL_BYPASS_ (0x0000001)
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#define RGMII_RX_BYP_DLL (0x70C)
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#define RGMII_RX_BYP_DLL_RX_TUNE_ADJ_MASK_ (0x000FC00)
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#define RGMII_RX_BYP_DLL_RX_TUNE_SEL_MASK_ (0x00003F0)
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#define RGMII_RX_BYP_DLL_RX_DLL_RESET_ (0x0000002)
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#define RGMII_RX_BYP_DLL_RX_DLL_BYPASS_ (0x0000001)
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#define OTP_BASE_ADDR (0x00001000)
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#define OTP_ADDR_RANGE_ (0x1FF)
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