ALSA: ctxfi: Change PLL initialization code
This is a reworked patch from Creative to change the PLL code to address unreliable 44100Hz initialization. Signed-off-by: Harry Butterworth <heb1001@gmail.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -1316,21 +1316,18 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr)
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pllenb = 0xB;
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hw_write_20kx(hw, PLL_ENB, pllenb);
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pllctl = 0x20D00000;
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set_field(&pllctl, PLLCTL_FD, 16 - 4);
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hw_write_20kx(hw, PLL_CTL, pllctl);
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mdelay(40);
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pllctl = hw_read_20kx(hw, PLL_CTL);
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pllctl = 0x20C00000;
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set_field(&pllctl, PLLCTL_B, 0);
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if (48000 == rsr) {
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set_field(&pllctl, PLLCTL_FD, 16 - 2);
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set_field(&pllctl, PLLCTL_RD, 1 - 1); /* 3000*16/1 = 48000 */
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} else { /* 44100 */
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set_field(&pllctl, PLLCTL_FD, 147 - 2);
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set_field(&pllctl, PLLCTL_RD, 10 - 1); /* 3000*147/10 = 44100 */
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}
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set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
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set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
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hw_write_20kx(hw, PLL_CTL, pllctl);
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mdelay(40);
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pllctl = hw_read_20kx(hw, PLL_CTL);
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set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
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hw_write_20kx(hw, PLL_CTL, pllctl);
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mdelay(40);
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for (i = 0; i < 1000; i++) {
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pllstat = hw_read_20kx(hw, PLL_STAT);
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if (get_field(pllstat, PLLSTAT_PD))
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