x86, mce, cmci: define MSR names and fields for new CMCI registers
Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -53,6 +53,7 @@
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#define APIC_ESR_SENDILL 0x00020
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#define APIC_ESR_RECVILL 0x00040
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#define APIC_ESR_ILLREGA 0x00080
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#define APIC_LVTCMCI 0x2f0
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#define APIC_ICR 0x300
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#define APIC_DEST_SELF 0x40000
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#define APIC_DEST_ALLINC 0x80000
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@ -11,6 +11,8 @@
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*/
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#define MCG_CTL_P (1UL<<8) /* MCG_CAP register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_STATUS_RIPV (1UL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1UL<<1) /* ip points to correct instruction */
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@ -77,6 +77,11 @@
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#define MSR_IA32_MC0_ADDR 0x00000402
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#define MSR_IA32_MC0_MISC 0x00000403
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/* These are consecutive and not in the normal 4er MCE bank block */
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#define MSR_IA32_MC0_CTL2 0x00000280
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#define CMCI_EN (1ULL << 30)
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#define CMCI_THRESHOLD_MASK 0xffffULL
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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