diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index c44aa974e79c..0929768573ba 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -595,6 +595,7 @@ comment "i.MX6 family:" config SOC_IMX6Q bool "i.MX6 Quad support" + select ARM_CPU_SUSPEND if PM select ARM_GIC select CACHE_L2X0 select CPU_V7 diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index aba73214c2a8..7a739bb5915e 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -70,4 +70,8 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o -obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o +obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o + +ifeq ($(CONFIG_PM),y) +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o +endif diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S index 6229efbc70cb..cec23a857c7e 100644 --- a/arch/arm/mach-imx/head-v7.S +++ b/arch/arm/mach-imx/head-v7.S @@ -71,6 +71,7 @@ ENTRY(v7_secondary_startup) ENDPROC(v7_secondary_startup) #endif +#ifdef CONFIG_PM /* * The following code is located into the .data section. This is to * allow phys_l2x0_saved_regs to be accessed with a relative load @@ -79,6 +80,7 @@ ENDPROC(v7_secondary_startup) .data .align +#ifdef CONFIG_CACHE_L2X0 .macro pl310_resume ldr r2, phys_l2x0_saved_regs ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0 @@ -88,12 +90,17 @@ ENDPROC(v7_secondary_startup) str r1, [r0, #L2X0_CTRL] @ re-enable L2 .endm + .globl phys_l2x0_saved_regs +phys_l2x0_saved_regs: + .long 0 +#else + .macro pl310_resume + .endm +#endif + ENTRY(v7_cpu_resume) bl v7_invalidate_l1 pl310_resume b cpu_resume ENDPROC(v7_cpu_resume) - - .globl phys_l2x0_saved_regs -phys_l2x0_saved_regs: - .long 0 +#endif diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index f20f191d7cca..f7b0c2b1b905 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -64,7 +64,9 @@ void __init imx6q_pm_init(void) * address of the data structure used by l2x0 core to save registers, * and later restore the necessary ones in imx6q resume entry. */ +#ifdef CONFIG_CACHE_L2X0 phys_l2x0_saved_regs = __pa(&l2x0_saved_regs); +#endif suspend_set_ops(&imx6q_pm_ops); } diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index df4a508f240a..bc17dfea3817 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -13,6 +13,7 @@ #include #include +#include #include @@ -21,10 +22,26 @@ #include #include +static struct clk *gpc_dvfs_clk; + static void imx5_idle(void) { - if (!need_resched()) + if (!need_resched()) { + /* gpc clock is needed for SRPG */ + if (gpc_dvfs_clk == NULL) { + gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs"); + if (IS_ERR(gpc_dvfs_clk)) + goto err0; + } + clk_enable(gpc_dvfs_clk); mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + if (tzic_enable_wake()) + goto err1; + cpu_do_idle(); +err1: + clk_disable(gpc_dvfs_clk); + } +err0: local_irq_enable(); } diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 144ebebc4a61..5eebfaad1226 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode) stop_mode = 1; } arm_srpgcr |= MXC_SRPGCR_PCR; - - if (tzic_enable_wake(1) != 0) - return; break; case STOP_POWER_ON: ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 6698cae942f7..3846c53f5b5d 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -130,6 +130,12 @@ extern void imx53_evk_common_init(void); extern void imx53_qsb_common_init(void); extern void imx53_smd_common_init(void); extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -extern void imx6q_pm_init(void); extern void imx6q_clock_map_io(void); + +#ifdef CONFIG_PM +extern void imx6q_pm_init(void); +#else +static inline void imx6q_pm_init(void) {} +#endif + #endif diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a4d36d601d55..d78298366a91 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -168,7 +168,7 @@ struct cpu_op { u32 cpu_rate; }; -int tzic_enable_wake(int is_idle); +int tzic_enable_wake(void); extern struct cpu_op *(*get_cpu_op)(int *op); #endif diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index a3c164c7ba82..98308ec1f321 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -73,7 +73,28 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type) #define tzic_set_irq_fiq NULL #endif -static unsigned int *wakeup_intr[4]; +#ifdef CONFIG_PM +static void tzic_irq_suspend(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + int idx = gc->irq_base >> 5; + + __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); +} + +static void tzic_irq_resume(struct irq_data *d) +{ + struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); + int idx = gc->irq_base >> 5; + + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), + tzic_base + TZIC_WAKEUP0(idx)); +} + +#else +#define tzic_irq_suspend NULL +#define tzic_irq_resume NULL +#endif static struct mxc_extra_irq tzic_extra_irq = { #ifdef CONFIG_FIQ @@ -91,12 +112,13 @@ static __init void tzic_init_gc(unsigned int irq_start) handle_level_irq); gc->private = &tzic_extra_irq; gc->wake_enabled = IRQ_MSK(32); - wakeup_intr[idx] = &gc->wake_active; ct = gc->chip_types; ct->chip.irq_mask = irq_gc_mask_disable_reg; ct->chip.irq_unmask = irq_gc_unmask_enable_reg; ct->chip.irq_set_wake = irq_gc_set_wake; + ct->chip.irq_suspend = tzic_irq_suspend; + ct->chip.irq_resume = tzic_irq_resume; ct->regs.disable = TZIC_ENCLEAR0(idx); ct->regs.enable = TZIC_ENSET0(idx); @@ -167,23 +189,19 @@ void __init tzic_init_irq(void __iomem *irqbase) /** * tzic_enable_wake() - enable wakeup interrupt * - * @param is_idle 1 if called in idle loop (ENSET0 register); - * 0 to be used when called from low power entry * @return 0 if successful; non-zero otherwise */ -int tzic_enable_wake(int is_idle) +int tzic_enable_wake(void) { - unsigned int i, v; + unsigned int i; __raw_writel(1, tzic_base + TZIC_DSMINT); if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) return -EAGAIN; - for (i = 0; i < 4; i++) { - v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) : - *wakeup_intr[i]; - __raw_writel(v, tzic_base + TZIC_WAKEUP0(i)); - } + for (i = 0; i < 4; i++) + __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), + tzic_base + TZIC_WAKEUP0(i)); return 0; }