c6x: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
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@ -101,7 +101,7 @@ struct clk {
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#define CLK_PLL BIT(2) /* PLL-derived clock */
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#define PRE_PLL BIT(3) /* source is before PLL mult/div */
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#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
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#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
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#define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */
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#define MAX_PLL_SYSCLKS 16
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@ -145,7 +145,7 @@ loop:
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spin_lock_irqsave(&cache_lock, flags);
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/*
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* If another cache operation is occuring
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* If another cache operation is occurring
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*/
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if (unlikely(imcr_get(wc_reg))) {
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spin_unlock_irqrestore(&cache_lock, flags);
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