ASoC: tlv320aic32x4: Add 96k sample rate
The TLV320AIC32x4 series supports 96ksps rates in hardware. This patch adds the necessary PLL divider values and clock settings to the table to make 96ksps work. Signed-off-by: Jeremy McDermond <nh6z@nh6z.net> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -159,7 +159,10 @@ static const struct aic32x4_rate_divs aic32x4_divs[] = {
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/* 48k rate */
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{AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
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{AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
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{AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
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{AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4},
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/* 96k rate */
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{AIC32X4_FREQ_25000000, 96000, 2, 7, 8643, 64, 4, 4, 64, 4, 4, 1},
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};
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static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
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@ -564,7 +567,7 @@ static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
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return 0;
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}
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#define AIC32X4_RATES SNDRV_PCM_RATE_8000_48000
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#define AIC32X4_RATES SNDRV_PCM_RATE_8000_96000
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#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
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| SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
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