ARM: socfpga: Add clock entries into device tree
Adds the main PLL clock groups for SOCFPGA into device tree file so that the clock framework to query the clock and clock rates appropriately. $cat /sys/kernel/debug/clk/clk_summary clock enable_cnt prepare_cnt rate --------------------------------------------------------------------- osc1 2 2 25000000 sdram_pll 0 0 400000000 s2f_usr2_clk 0 0 66666666 ddr_dq_clk 0 0 200000000 ddr_2x_dqs_clk 0 0 400000000 ddr_dqs_clk 0 0 200000000 periph_pll 2 2 500000000 s2f_usr1_clk 0 0 50000000 per_base_clk 4 4 100000000 per_nand_mmc_clk 0 0 25000000 per_qsi_clk 0 0 250000000 emac1_clk 1 1 125000000 emac0_clk 0 0 125000000 main_pll 1 1 1600000000 cfg_s2f_usr0_clk 0 0 100000000 main_nand_sdmmc_clk 0 0 100000000 main_qspi_clk 0 0 400000000 dbg_base_clk 0 0 400000000 mainclk 0 0 400000000 mpuclk 1 1 800000000 smp_twd 1 1 200000000 Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Signed-off-by: Olof Johansson <olof@lixom.net>
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Altera SOCFPGA Clock Manager
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Required properties:
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- compatible : "altr,clk-mgr"
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- reg : Should contain base address and length for Clock Manager
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Example:
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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};
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Documentation/devicetree/bindings/clock/altr_socfpga.txt
Normal file
18
Documentation/devicetree/bindings/clock/altr_socfpga.txt
Normal file
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Device Tree Clock bindings for Altera's SoCFPGA platform
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be one of the following:
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"altr,socfpga-pll-clock" - for a PLL clock
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"altr,socfpga-perip-clock" - The peripheral clock divided from the
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PLL clock.
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- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
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- clocks : shall be the input parent clock phandle for the clock. This is
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either an oscillator or a pll output.
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- #clock-cells : from common clock binding, shall be set to 0.
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Optional properties:
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- fixed-divider : If clocks have a fixed divider value, use this property.
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};
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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main_pll: main_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc>;
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reg = <0x40>;
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mpuclk: mpuclk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <2>;
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reg = <0x48>;
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};
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mainclk: mainclk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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reg = <0x4C>;
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};
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dbg_base_clk: dbg_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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fixed-divider = <4>;
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reg = <0x50>;
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};
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main_qspi_clk: main_qspi_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x54>;
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};
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main_nand_sdmmc_clk: main_nand_sdmmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x58>;
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};
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cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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reg = <0x5C>;
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};
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};
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periph_pll: periph_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc>;
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reg = <0x80>;
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emac0_clk: emac0_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x88>;
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};
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emac1_clk: emac1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x8C>;
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};
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per_qspi_clk: per_qsi_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x90>;
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};
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per_nand_mmc_clk: per_nand_mmc_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x94>;
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};
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per_base_clk: per_base_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x98>;
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};
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s2f_usr1_clk: s2f_usr1_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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reg = <0x9C>;
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};
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};
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sdram_pll: sdram_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc>;
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reg = <0xC0>;
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ddr_dqs_clk: ddr_dqs_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xC8>;
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};
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ddr_2x_dqs_clk: ddr_2x_dqs_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xCC>;
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};
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ddr_dq_clk: ddr_dq_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xD0>;
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};
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s2f_usr2_clk: s2f_usr2_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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reg = <0xD4>;
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};
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};
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};
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};
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gmac0: stmmac@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xff700000 0x2000>;
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <10000000>;
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};
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};
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};
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timer0@ffc08000 {
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clock-frequency = <7000000>;
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};
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