powerpc/book3s: Add flush_tlb operation in cpu_spec.
This patch introduces flush_tlb operation in cpu_spec structure. This will help us to invoke appropriate CPU-side flush tlb routine. This patch adds the foundation to invoke CPU specific flush routine for respective architectures. Currently this patch introduce flush_tlb for p7 and p8. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Acked-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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4c703416ef
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0440705049
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@ -97,6 +97,11 @@ struct cpu_spec {
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*/
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long (*machine_check_early)(struct pt_regs *regs);
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/*
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* Processor specific routine to flush tlbs.
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*/
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void (*flush_tlb)(unsigned long inval_selector);
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};
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extern struct cpu_spec *cur_cpu_spec;
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@ -29,7 +29,7 @@ _GLOBAL(__setup_cpu_power7)
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mtspr SPRN_LPID,r0
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mfspr r3,SPRN_LPCR
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bl __init_LPCR
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bl __init_TLB
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bl __init_tlb_power7
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mtlr r11
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blr
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@ -42,7 +42,7 @@ _GLOBAL(__restore_cpu_power7)
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mtspr SPRN_LPID,r0
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mfspr r3,SPRN_LPCR
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bl __init_LPCR
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bl __init_TLB
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bl __init_tlb_power7
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mtlr r11
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blr
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@ -59,7 +59,7 @@ _GLOBAL(__setup_cpu_power8)
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oris r3, r3, LPCR_AIL_3@h
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bl __init_LPCR
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bl __init_HFSCR
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bl __init_TLB
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bl __init_tlb_power8
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bl __init_PMU_HV
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mtlr r11
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blr
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@ -78,7 +78,7 @@ _GLOBAL(__restore_cpu_power8)
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oris r3, r3, LPCR_AIL_3@h
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bl __init_LPCR
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bl __init_HFSCR
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bl __init_TLB
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bl __init_tlb_power8
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bl __init_PMU_HV
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mtlr r11
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blr
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@ -134,15 +134,31 @@ __init_HFSCR:
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mtspr SPRN_HFSCR,r3
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blr
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__init_TLB:
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/*
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* Clear the TLB using the "IS 3" form of tlbiel instruction
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* (invalidate by congruence class). P7 has 128 CCs, P8 has 512
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* so we just always do 512
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*/
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/*
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* Clear the TLB using the specified IS form of tlbiel instruction
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* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
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*
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* r3 = IS field
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*/
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__init_tlb_power7:
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li r3,0xc00 /* IS field = 0b11 */
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_GLOBAL(__flush_tlb_power7)
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li r6,128
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mtctr r6
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mr r7,r3 /* IS field */
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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bdnz 2b
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ptesync
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1: blr
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__init_tlb_power8:
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li r3,0xc00 /* IS field = 0b11 */
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_GLOBAL(__flush_tlb_power8)
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li r6,512
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mtctr r6
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li r7,0xc00 /* IS field = 0b11 */
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mr r7,r3 /* IS field */
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ptesync
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2: tlbiel r7
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addi r7,r7,0x1000
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@ -71,6 +71,8 @@ extern void __restore_cpu_power7(void);
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extern void __setup_cpu_power8(unsigned long offset, struct cpu_spec* spec);
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extern void __restore_cpu_power8(void);
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extern void __restore_cpu_a2(void);
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extern void __flush_tlb_power7(unsigned long inval_selector);
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extern void __flush_tlb_power8(unsigned long inval_selector);
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#endif /* CONFIG_PPC64 */
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#if defined(CONFIG_E500)
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extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
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@ -440,6 +442,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_cpu_type = "ppc64/ibm-compat-v1",
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.platform = "power7",
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},
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{ /* 2.07-compliant processor, i.e. Power8 "architected" mode */
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@ -456,6 +459,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_cpu_type = "ppc64/ibm-compat-v1",
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.cpu_setup = __setup_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.flush_tlb = __flush_tlb_power8,
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.platform = "power8",
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},
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{ /* Power7 */
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@ -474,6 +478,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_type = PPC_OPROFILE_POWER4,
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.platform = "power7",
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},
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{ /* Power7+ */
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@ -492,6 +497,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_type = PPC_OPROFILE_POWER4,
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.cpu_setup = __setup_cpu_power7,
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.cpu_restore = __restore_cpu_power7,
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.flush_tlb = __flush_tlb_power7,
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.platform = "power7+",
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},
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{ /* Power8E */
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@ -510,6 +516,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_type = PPC_OPROFILE_INVALID,
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.cpu_setup = __setup_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.flush_tlb = __flush_tlb_power8,
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.platform = "power8",
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},
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{ /* Power8 */
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@ -528,6 +535,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
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.oprofile_type = PPC_OPROFILE_INVALID,
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.cpu_setup = __setup_cpu_power8,
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.cpu_restore = __restore_cpu_power8,
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.flush_tlb = __flush_tlb_power8,
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.platform = "power8",
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},
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{ /* Cell Broadband Engine */
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@ -58,18 +58,6 @@ static void reload_slb(struct kvm_vcpu *vcpu)
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}
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}
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/* POWER7 TLB flush */
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static void flush_tlb_power7(struct kvm_vcpu *vcpu)
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{
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unsigned long i, rb;
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rb = TLBIEL_INVAL_SET_LPID;
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for (i = 0; i < POWER7_TLB_SETS; ++i) {
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asm volatile("tlbiel %0" : : "r" (rb));
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rb += 1 << TLBIEL_INVAL_SET_SHIFT;
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}
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}
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/*
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* On POWER7, see if we can handle a machine check that occurred inside
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* the guest in real mode, without switching to the host partition.
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@ -96,7 +84,8 @@ static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
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DSISR_MC_SLB_PARITY | DSISR_MC_DERAT_MULTI);
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}
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if (dsisr & DSISR_MC_TLB_MULTI) {
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flush_tlb_power7(vcpu);
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET_LPID);
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dsisr &= ~DSISR_MC_TLB_MULTI;
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}
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/* Any other errors we don't understand? */
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@ -113,7 +102,8 @@ static long kvmppc_realmode_mc_power7(struct kvm_vcpu *vcpu)
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reload_slb(vcpu);
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break;
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case SRR1_MC_IFETCH_TLBMULTI:
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flush_tlb_power7(vcpu);
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if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
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cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET_LPID);
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break;
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default:
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handled = 0;
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