dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63
[ Upstream commit d087f15786
]
Register layout of a typical TPCC_EVT_MUX_M_N register is such that the
lowest numbered event is at the lowest byte address and highest numbered
event at highest byte address. But TPCC_EVT_MUX_60_63 register layout is
different, in that the lowest numbered event is at the highest address
and highest numbered event is at the lowest address. Therefore, modify
ti_am335x_xbar_write() to handle TPCC_EVT_MUX_60_63 register
accordingly.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pull/10/head
parent
e618ff1ac5
commit
0493d72ee4
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@ -54,7 +54,15 @@ struct ti_am335x_xbar_map {
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static inline void ti_am335x_xbar_write(void __iomem *iomem, int event, u8 val)
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{
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writeb_relaxed(val, iomem + event);
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/*
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* TPCC_EVT_MUX_60_63 register layout is different than the
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* rest, in the sense, that event 63 is mapped to lowest byte
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* and event 60 is mapped to highest, handle it separately.
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*/
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if (event >= 60 && event <= 63)
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writeb_relaxed(val, iomem + (63 - event % 4));
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else
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writeb_relaxed(val, iomem + event);
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}
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static void ti_am335x_xbar_free(struct device *dev, void *route_data)
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