clk:SPEAr1340: Correct parent clock configuration
This patch corrects wrongly configured parent clock for following devices: * Video enc/decoder * Video ip * Pin control * ACP * camx Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -960,47 +960,47 @@ void __init spear1340_clk_init(void)
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SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
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clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
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clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
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clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
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SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "acp_clk");
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clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
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clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "e2800000.gpio");
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clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
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clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
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0, &_lock);
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clk_register_clkdev(clk, NULL, "video_dec");
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clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0,
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clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
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0, &_lock);
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clk_register_clkdev(clk, NULL, "video_enc");
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clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0,
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clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "spear_vip");
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clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
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clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "d0200000.cam0");
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clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
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clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "d0300000.cam1");
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clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
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clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "d0400000.cam2");
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clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
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clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
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SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
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&_lock);
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clk_register_clkdev(clk, NULL, "d0500000.cam3");
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