staging: pi433: Style fix - align block comments
Fixed the alignment of block comments Found using checkpatch Signed-off-by: Derek Robson <robsonde@gmail.com> Reviewed-by: Marcus Wolf <linux@wolf-entwicklungen.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>zero-colors
Derek Robson
Greg Kroah-Hartman
parent
775f6ab013
commit
056eeda2f9
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@ -67,9 +67,11 @@ static DEFINE_MUTEX(minor_lock); /* Protect idr accesses */
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static struct class *pi433_class; /* mainly for udev to create /dev/pi433 */
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/* tx config is instance specific
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so with each open a new tx config struct is needed */
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* so with each open a new tx config struct is needed
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*/
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/* rx config is device specific
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so we have just one rx config, ebedded in device struct */
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* so we have just one rx config, ebedded in device struct
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*/
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struct pi433_device {
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/* device handling related values */
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dev_t devt;
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@ -486,9 +488,10 @@ pi433_tx_thread(void *data)
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return 0;
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/* get data from fifo in the following order:
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- tx_cfg
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- size of message
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- message */
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* - tx_cfg
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* - size of message
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* - message
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*/
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mutex_lock(&device->tx_fifo_lock);
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retval = kfifo_out(&device->tx_fifo, &tx_cfg, sizeof(tx_cfg));
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@ -537,23 +540,26 @@ pi433_tx_thread(void *data)
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mutex_unlock(&device->tx_fifo_lock);
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/* if rx is active, we need to interrupt the waiting for
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incoming telegrams, to be able to send something.
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We are only allowed, if currently no reception takes
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place otherwise we need to wait for the incoming telegram
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to finish */
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* incoming telegrams, to be able to send something.
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* We are only allowed, if currently no reception takes
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* place otherwise we need to wait for the incoming telegram
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* to finish
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*/
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wait_event_interruptible(device->tx_wait_queue,
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!device->rx_active ||
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device->interrupt_rx_allowed == true);
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/* prevent race conditions
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irq will be reenabled after tx config is set */
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* irq will be reenabled after tx config is set
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*/
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disable_irq(device->irq_num[DIO0]);
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device->tx_active = true;
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if (device->rx_active && rx_interrupted == false)
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{
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/* rx is currently waiting for a telegram;
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we need to set the radio module to standby */
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* we need to set the radio module to standby
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*/
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SET_CHECKED(rf69_set_mode(device->spi, standby));
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rx_interrupted = true;
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}
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@ -712,9 +718,10 @@ pi433_write(struct file *filp, const char __user *buf,
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return -EMSGSIZE;
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/* write the following sequence into fifo:
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- tx_cfg
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- size of message
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- message */
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* - tx_cfg
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* - size of message
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* - message
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*/
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mutex_lock(&device->tx_fifo_lock);
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retval = kfifo_in(&device->tx_fifo, &instance->tx_cfg, sizeof(instance->tx_cfg));
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if ( retval != sizeof(instance->tx_cfg) )
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@ -1269,7 +1276,8 @@ static int __init pi433_init(void)
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int status;
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/* If MAX_MSG_SIZE is smaller then FIFO_SIZE, the driver won't
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work stable - risk of buffer overflow */
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* work stable - risk of buffer overflow
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*/
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if (MAX_MSG_SIZE < FIFO_SIZE)
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return -EINVAL;
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@ -940,8 +940,9 @@ u8 rf69_read_reg(struct spi_device *spi, u8 addr)
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#ifdef DEBUG_VALUES
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if (retval < 0)
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/* should never happen, since we already checked,
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that module is connected. Therefore no error
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handling, just an optional error message... */
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* that module is connected. Therefore no error
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* handling, just an optional error message...
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*/
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dev_dbg(&spi->dev, "read 0x%x FAILED\n",
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addr);
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else
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@ -966,8 +967,9 @@ int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value)
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#ifdef DEBUG_VALUES
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if (retval < 0)
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/* should never happen, since we already checked,
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that module is connected. Therefore no error
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handling, just an optional error message... */
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* that module is connected. Therefore no error
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* handling, just an optional error message...
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*/
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dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n",
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value,
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addr);
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@ -143,44 +143,44 @@
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#define FDEVMASB_MASK 0x3f
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/*
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// RegOsc1
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#define OSC1_RCCAL_START 0x80
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#define OSC1_RCCAL_DONE 0x40
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// RegLowBat
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#define LOWBAT_MONITOR 0x10
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#define LOWBAT_ON 0x08
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#define LOWBAT_OFF 0x00 // Default
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#define LOWBAT_TRIM_1695 0x00
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#define LOWBAT_TRIM_1764 0x01
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#define LOWBAT_TRIM_1835 0x02 // Default
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#define LOWBAT_TRIM_1905 0x03
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#define LOWBAT_TRIM_1976 0x04
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#define LOWBAT_TRIM_2045 0x05
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#define LOWBAT_TRIM_2116 0x06
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#define LOWBAT_TRIM_2185 0x07
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// RegListen1
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#define LISTEN1_RESOL_64 0x50
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#define LISTEN1_RESOL_4100 0xA0 // Default
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#define LISTEN1_RESOL_262000 0xF0
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#define LISTEN1_CRITERIA_RSSI 0x00 // Default
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#define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
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#define LISTEN1_END_00 0x00
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#define LISTEN1_END_01 0x02 // Default
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#define LISTEN1_END_10 0x04
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// RegListen2
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#define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
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// RegListen3
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#define LISTEN3_COEFRX_VALUE 0x20 // Default
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*/
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* // RegOsc1
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* #define OSC1_RCCAL_START 0x80
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* #define OSC1_RCCAL_DONE 0x40
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*
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* // RegLowBat
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* #define LOWBAT_MONITOR 0x10
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* #define LOWBAT_ON 0x08
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* #define LOWBAT_OFF 0x00 // Default
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*
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* #define LOWBAT_TRIM_1695 0x00
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* #define LOWBAT_TRIM_1764 0x01
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* #define LOWBAT_TRIM_1835 0x02 // Default
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* #define LOWBAT_TRIM_1905 0x03
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* #define LOWBAT_TRIM_1976 0x04
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* #define LOWBAT_TRIM_2045 0x05
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* #define LOWBAT_TRIM_2116 0x06
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* #define LOWBAT_TRIM_2185 0x07
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*
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*
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* // RegListen1
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* #define LISTEN1_RESOL_64 0x50
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* #define LISTEN1_RESOL_4100 0xA0 // Default
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* #define LISTEN1_RESOL_262000 0xF0
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*
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* #define LISTEN1_CRITERIA_RSSI 0x00 // Default
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* #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
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*
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* #define LISTEN1_END_00 0x00
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* #define LISTEN1_END_01 0x02 // Default
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* #define LISTEN1_END_10 0x04
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*
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*
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* // RegListen2
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* #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
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*
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* // RegListen3
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* #define LISTEN3_COEFRX_VALUE 0x20 // Default
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*/
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// RegPaLevel
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#define MASK_PALEVEL_PA0 0x80
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@ -211,27 +211,27 @@
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#define MASK_PARAMP 0x0F
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/*
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// RegOcp
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#define OCP_OFF 0x0F
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#define OCP_ON 0x1A // Default
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#define OCP_TRIM_45 0x00
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#define OCP_TRIM_50 0x01
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#define OCP_TRIM_55 0x02
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#define OCP_TRIM_60 0x03
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#define OCP_TRIM_65 0x04
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#define OCP_TRIM_70 0x05
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#define OCP_TRIM_75 0x06
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#define OCP_TRIM_80 0x07
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#define OCP_TRIM_85 0x08
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#define OCP_TRIM_90 0x09
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#define OCP_TRIM_95 0x0A
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#define OCP_TRIM_100 0x0B // Default
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#define OCP_TRIM_105 0x0C
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#define OCP_TRIM_110 0x0D
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#define OCP_TRIM_115 0x0E
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#define OCP_TRIM_120 0x0F
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*/
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* // RegOcp
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* #define OCP_OFF 0x0F
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* #define OCP_ON 0x1A // Default
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*
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* #define OCP_TRIM_45 0x00
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* #define OCP_TRIM_50 0x01
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* #define OCP_TRIM_55 0x02
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* #define OCP_TRIM_60 0x03
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* #define OCP_TRIM_65 0x04
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* #define OCP_TRIM_70 0x05
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* #define OCP_TRIM_75 0x06
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* #define OCP_TRIM_80 0x07
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* #define OCP_TRIM_85 0x08
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* #define OCP_TRIM_90 0x09
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* #define OCP_TRIM_95 0x0A
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* #define OCP_TRIM_100 0x0B // Default
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* #define OCP_TRIM_105 0x0C
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* #define OCP_TRIM_110 0x0D
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* #define OCP_TRIM_115 0x0E
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* #define OCP_TRIM_120 0x0F
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*/
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/* RegLna (0x18) */
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#define MASK_LNA_ZIN 0x80
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@ -294,32 +294,32 @@
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#define OOKPEAK_THRESHDEC_16_TIMES 0x07
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/*
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// RegOokAvg
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#define OOKAVG_AVERAGETHRESHFILT_00 0x00
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#define OOKAVG_AVERAGETHRESHFILT_01 0x40
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#define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
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#define OOKAVG_AVERAGETHRESHFILT_11 0xC0
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// RegAfcFei
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#define AFCFEI_FEI_DONE 0x40
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#define AFCFEI_FEI_START 0x20
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#define AFCFEI_AFC_DONE 0x10
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#define AFCFEI_AFCAUTOCLEAR_ON 0x08
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#define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
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#define AFCFEI_AFCAUTO_ON 0x04
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#define AFCFEI_AFCAUTO_OFF 0x00 // Default
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#define AFCFEI_AFC_CLEAR 0x02
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#define AFCFEI_AFC_START 0x01
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// RegRssiConfig
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#define RSSI_FASTRX_ON 0x08
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#define RSSI_FASTRX_OFF 0x00 // Default
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#define RSSI_DONE 0x02
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#define RSSI_START 0x01
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*/
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* // RegOokAvg
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* #define OOKAVG_AVERAGETHRESHFILT_00 0x00
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* #define OOKAVG_AVERAGETHRESHFILT_01 0x40
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* #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
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* #define OOKAVG_AVERAGETHRESHFILT_11 0xC0
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*
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*
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* // RegAfcFei
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* #define AFCFEI_FEI_DONE 0x40
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* #define AFCFEI_FEI_START 0x20
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* #define AFCFEI_AFC_DONE 0x10
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* #define AFCFEI_AFCAUTOCLEAR_ON 0x08
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* #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
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*
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* #define AFCFEI_AFCAUTO_ON 0x04
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* #define AFCFEI_AFCAUTO_OFF 0x00 // Default
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*
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* #define AFCFEI_AFC_CLEAR 0x02
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* #define AFCFEI_AFC_START 0x01
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*
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* // RegRssiConfig
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* #define RSSI_FASTRX_ON 0x08
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* #define RSSI_FASTRX_OFF 0x00 // Default
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* #define RSSI_DONE 0x02
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* #define RSSI_START 0x01
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*/
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/* RegDioMapping1 */
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#define MASK_DIO0 0xC0
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@ -422,66 +422,66 @@
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#define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04
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/*
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// RegAutoModes
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#define AUTOMODES_ENTER_OFF 0x00 // Default
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#define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
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#define AUTOMODES_ENTER_FIFOLEVEL 0x40
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#define AUTOMODES_ENTER_CRCOK 0x60
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#define AUTOMODES_ENTER_PAYLOADREADY 0x80
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#define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
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#define AUTOMODES_ENTER_PACKETSENT 0xC0
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#define AUTOMODES_ENTER_FIFOEMPTY 0xE0
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#define AUTOMODES_EXIT_OFF 0x00 // Default
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#define AUTOMODES_EXIT_FIFOEMPTY 0x04
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#define AUTOMODES_EXIT_FIFOLEVEL 0x08
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#define AUTOMODES_EXIT_CRCOK 0x0C
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#define AUTOMODES_EXIT_PAYLOADREADY 0x10
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#define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
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#define AUTOMODES_EXIT_PACKETSENT 0x18
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#define AUTOMODES_EXIT_RXTIMEOUT 0x1C
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#define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
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#define AUTOMODES_INTERMEDIATE_STANDBY 0x01
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#define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
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#define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
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*/
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* // RegAutoModes
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* #define AUTOMODES_ENTER_OFF 0x00 // Default
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* #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
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* #define AUTOMODES_ENTER_FIFOLEVEL 0x40
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* #define AUTOMODES_ENTER_CRCOK 0x60
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* #define AUTOMODES_ENTER_PAYLOADREADY 0x80
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* #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
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* #define AUTOMODES_ENTER_PACKETSENT 0xC0
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* #define AUTOMODES_ENTER_FIFOEMPTY 0xE0
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*
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* #define AUTOMODES_EXIT_OFF 0x00 // Default
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* #define AUTOMODES_EXIT_FIFOEMPTY 0x04
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* #define AUTOMODES_EXIT_FIFOLEVEL 0x08
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* #define AUTOMODES_EXIT_CRCOK 0x0C
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* #define AUTOMODES_EXIT_PAYLOADREADY 0x10
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* #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
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* #define AUTOMODES_EXIT_PACKETSENT 0x18
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* #define AUTOMODES_EXIT_RXTIMEOUT 0x1C
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*
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* #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
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* #define AUTOMODES_INTERMEDIATE_STANDBY 0x01
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* #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
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* #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
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*
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*/
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/* RegFifoThresh (0x3c) */
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#define MASK_FIFO_THRESH_TXSTART 0x80
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#define MASK_FIFO_THRESH_VALUE 0x7F
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/*
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// RegPacketConfig2
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#define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
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#define PACKET2_RXRESTARTDELAY_2BITS 0x10
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#define PACKET2_RXRESTARTDELAY_4BITS 0x20
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#define PACKET2_RXRESTARTDELAY_8BITS 0x30
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#define PACKET2_RXRESTARTDELAY_16BITS 0x40
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#define PACKET2_RXRESTARTDELAY_32BITS 0x50
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#define PACKET2_RXRESTARTDELAY_64BITS 0x60
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#define PACKET2_RXRESTARTDELAY_128BITS 0x70
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#define PACKET2_RXRESTARTDELAY_256BITS 0x80
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#define PACKET2_RXRESTARTDELAY_512BITS 0x90
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#define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
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#define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
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#define PACKET2_RXRESTARTDELAY_NONE 0xC0
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#define PACKET2_RXRESTART 0x04
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#define PACKET2_AUTORXRESTART_ON 0x02 // Default
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#define PACKET2_AUTORXRESTART_OFF 0x00
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#define PACKET2_AES_ON 0x01
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#define PACKET2_AES_OFF 0x00 // Default
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// RegTemp1
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#define TEMP1_MEAS_START 0x08
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#define TEMP1_MEAS_RUNNING 0x04
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#define TEMP1_ADCLOWPOWER_ON 0x01 // Default
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#define TEMP1_ADCLOWPOWER_OFF 0x00
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*/
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*
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* // RegPacketConfig2
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* #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
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* #define PACKET2_RXRESTARTDELAY_2BITS 0x10
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* #define PACKET2_RXRESTARTDELAY_4BITS 0x20
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* #define PACKET2_RXRESTARTDELAY_8BITS 0x30
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* #define PACKET2_RXRESTARTDELAY_16BITS 0x40
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* #define PACKET2_RXRESTARTDELAY_32BITS 0x50
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* #define PACKET2_RXRESTARTDELAY_64BITS 0x60
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* #define PACKET2_RXRESTARTDELAY_128BITS 0x70
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* #define PACKET2_RXRESTARTDELAY_256BITS 0x80
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* #define PACKET2_RXRESTARTDELAY_512BITS 0x90
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* #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
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* #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
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* #define PACKET2_RXRESTARTDELAY_NONE 0xC0
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* #define PACKET2_RXRESTART 0x04
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*
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||||
* #define PACKET2_AUTORXRESTART_ON 0x02 // Default
|
||||
* #define PACKET2_AUTORXRESTART_OFF 0x00
|
||||
*
|
||||
* #define PACKET2_AES_ON 0x01
|
||||
* #define PACKET2_AES_OFF 0x00 // Default
|
||||
*
|
||||
*
|
||||
* // RegTemp1
|
||||
* #define TEMP1_MEAS_START 0x08
|
||||
* #define TEMP1_MEAS_RUNNING 0x04
|
||||
* #define TEMP1_ADCLOWPOWER_ON 0x01 // Default
|
||||
* #define TEMP1_ADCLOWPOWER_OFF 0x00
|
||||
*/
|
||||
|
||||
// RegTestDagc (0x6F)
|
||||
#define DAGC_NORMAL 0x00 /* Reset value */
|
||||
|
|
|
|||
Loading…
Reference in New Issue