sparc64: T5 PMU
The T5 (niagara5) has different PCR related HV fast trap values and a new HV API Group. This patch utilizes these and shares when possible with niagara4. We use the same sparc_pmu niagara4_pmu. Should there be new effort to obtain the MCU perf statistics then this would have to be changed. Cc: sparclinux@vger.kernel.org Signed-off-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2947,6 +2947,16 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
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unsigned long reg_val);
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#endif
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#define HV_FAST_T5_GET_PERFREG 0x1a8
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#define HV_FAST_T5_SET_PERFREG 0x1a9
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#ifndef __ASSEMBLY__
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unsigned long sun4v_t5_get_perfreg(unsigned long reg_num,
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unsigned long *reg_val);
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unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
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unsigned long reg_val);
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#endif
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/* Function numbers for HV_CORE_TRAP. */
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#define HV_CORE_SET_VER 0x00
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#define HV_CORE_PUTCHAR 0x01
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@ -2978,6 +2988,7 @@ unsigned long sun4v_vt_set_perfreg(unsigned long reg_num,
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#define HV_GRP_VF_CPU 0x0205
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#define HV_GRP_KT_CPU 0x0209
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#define HV_GRP_VT_CPU 0x020c
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#define HV_GRP_T5_CPU 0x0211
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#define HV_GRP_DIAG 0x0300
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#ifndef __ASSEMBLY__
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@ -46,6 +46,7 @@ static struct api_info api_table[] = {
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{ .group = HV_GRP_VF_CPU, },
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{ .group = HV_GRP_KT_CPU, },
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{ .group = HV_GRP_VT_CPU, },
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{ .group = HV_GRP_T5_CPU, },
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{ .group = HV_GRP_DIAG, .flags = FLAG_PRE_API },
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};
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@ -821,3 +821,19 @@ ENTRY(sun4v_vt_set_perfreg)
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retl
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nop
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ENDPROC(sun4v_vt_set_perfreg)
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ENTRY(sun4v_t5_get_perfreg)
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mov %o1, %o4
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mov HV_FAST_T5_GET_PERFREG, %o5
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ta HV_FAST_TRAP
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stx %o1, [%o4]
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retl
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nop
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ENDPROC(sun4v_t5_get_perfreg)
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ENTRY(sun4v_t5_set_perfreg)
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mov HV_FAST_T5_SET_PERFREG, %o5
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ta HV_FAST_TRAP
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retl
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nop
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ENDPROC(sun4v_t5_set_perfreg)
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@ -191,12 +191,41 @@ static const struct pcr_ops n4_pcr_ops = {
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.pcr_nmi_disable = PCR_N4_PICNPT,
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};
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static u64 n5_pcr_read(unsigned long reg_num)
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{
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unsigned long val;
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(void) sun4v_t5_get_perfreg(reg_num, &val);
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return val;
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}
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static void n5_pcr_write(unsigned long reg_num, u64 val)
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{
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(void) sun4v_t5_set_perfreg(reg_num, val);
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}
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static const struct pcr_ops n5_pcr_ops = {
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.read_pcr = n5_pcr_read,
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.write_pcr = n5_pcr_write,
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.read_pic = n4_pic_read,
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.write_pic = n4_pic_write,
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.nmi_picl_value = n4_picl_value,
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.pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
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PCR_N4_UTRACE | PCR_N4_TOE |
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(26 << PCR_N4_SL_SHIFT)),
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.pcr_nmi_disable = PCR_N4_PICNPT,
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};
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static unsigned long perf_hsvc_group;
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static unsigned long perf_hsvc_major;
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static unsigned long perf_hsvc_minor;
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static int __init register_perf_hsvc(void)
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{
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unsigned long hverror;
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if (tlb_type == hypervisor) {
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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@ -215,6 +244,10 @@ static int __init register_perf_hsvc(void)
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perf_hsvc_group = HV_GRP_VT_CPU;
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break;
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case SUN4V_CHIP_NIAGARA5:
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perf_hsvc_group = HV_GRP_T5_CPU;
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break;
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default:
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return -ENODEV;
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}
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@ -222,10 +255,12 @@ static int __init register_perf_hsvc(void)
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perf_hsvc_major = 1;
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perf_hsvc_minor = 0;
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if (sun4v_hvapi_register(perf_hsvc_group,
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perf_hsvc_major,
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&perf_hsvc_minor)) {
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printk("perfmon: Could not register hvapi.\n");
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hverror = sun4v_hvapi_register(perf_hsvc_group,
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perf_hsvc_major,
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&perf_hsvc_minor);
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if (hverror) {
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pr_err("perfmon: Could not register hvapi(0x%lx).\n",
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hverror);
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return -ENODEV;
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}
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}
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@ -254,6 +289,10 @@ static int __init setup_sun4v_pcr_ops(void)
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pcr_ops = &n4_pcr_ops;
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break;
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case SUN4V_CHIP_NIAGARA5:
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pcr_ops = &n5_pcr_ops;
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break;
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default:
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ret = -ENODEV;
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break;
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@ -1662,7 +1662,8 @@ static bool __init supported_pmu(void)
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sparc_pmu = &niagara2_pmu;
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return true;
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}
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if (!strcmp(sparc_pmu_type, "niagara4")) {
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if (!strcmp(sparc_pmu_type, "niagara4") ||
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!strcmp(sparc_pmu_type, "niagara5")) {
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sparc_pmu = &niagara4_pmu;
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return true;
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}
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