ARM: dts: imx6qdl: Fix "WARNING: please, no space before tabs"
Fixed no space before tabs warnings in respetcive imx6qdl dtsi files. Signed-off-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
parent
371a8dd6fa
commit
05c183e44b
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@ -347,13 +347,13 @@
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
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MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
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MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
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MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
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MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
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MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
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MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
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MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
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MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
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MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
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MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
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MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
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MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
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MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
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MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
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MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
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MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
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MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
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>;
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>;
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};
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};
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@ -429,8 +429,8 @@
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pinctrl_edt_ft5x06: edt-ft5x06grp {
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pinctrl_edt_ft5x06: edt-ft5x06grp {
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
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MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
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MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
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MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
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MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
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MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
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>;
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>;
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};
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};
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@ -481,21 +481,21 @@
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pinctrl_gpmi_nand: gpminandgrp {
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pinctrl_gpmi_nand: gpminandgrp {
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
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MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
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MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
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MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
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MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
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MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
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MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
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MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
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MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
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MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
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MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
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MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
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MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
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MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
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MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
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MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
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>;
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>;
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};
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};
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@ -129,8 +129,8 @@
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pinctrl_i2c1: i2c1grp {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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>;
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};
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};
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